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lal87 |
----------------------------------------------------------------------------
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---- Create Date: 19:12:45 10/24/2010 ----
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---- Design Name: pic_tb ----
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---- Project Name: PIC ----
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---- Description: ----
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---- A testbench code for the pic.vhd code ----
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---- ----
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----------------------------------------------------------------------------
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---- ----
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---- This file is a part of the pic project at ----
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---- http://www.opencores.org/ ----
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---- ----
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---- Author(s): ----
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---- Vipin Lal, lalnitt@gmail.com ----
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---- ----
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----------------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2010 Authors and OPENCORES.ORG ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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----------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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ENTITY pic_tb IS
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END pic_tb;
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ARCHITECTURE behavior OF pic_tb IS
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT PIC
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PORT(
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CLK_I : IN std_logic;
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RST_I : IN std_logic;
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IR : IN unsigned(7 downto 0);
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DataBus : INOUT unsigned(7 downto 0);
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INTR_O : OUT std_logic;
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INTA_I : IN std_logic
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);
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END COMPONENT;
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--Inputs
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signal CLK_I : std_logic := '0';
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signal RST_I : std_logic := '0';
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signal IR : unsigned(7 downto 0) := (others => '0');
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signal INTA_I : std_logic := '1';
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--BiDirs
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signal DataBus : unsigned(7 downto 0);
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--Outputs
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signal INTR_O : std_logic;
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-- Clock period definitions
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constant CLK_period : time := 10 ns;
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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uut: PIC PORT MAP (
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CLK_I => CLK_I,
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RST_I => RST_I,
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IR => IR,
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DataBus => DataBus,
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INTR_O => INTR_O,
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INTA_I => INTA_I
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);
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-- Clock process definitions
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CLK_I_process :process
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begin
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CLK_I <= '0';
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wait for CLK_period/2;
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CLK_I <= '1';
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wait for CLK_period/2;
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end process;
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-- Stimulus process.
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stim_proc: process
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begin
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DataBus <= (others => 'Z');
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RST_I <= '1';
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wait for clk_period;
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RST_I <= '0';
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wait for clk_period*3;
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DataBus(1 downto 0) <= "01"; --set polling method.
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wait for clk_period;
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DataBus <= (others => 'Z'); --make databus as high impedance.
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wait until INTR_O = '1'; --wait for an interrupt.
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wait for clk_period;
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INTA_I <= '0'; --send ack in the next clk cycle.
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wait for clk_period;
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INTA_I <= '1'; --reset ack.
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wait until DataBus = "01011011"; --wait till info abt interrupt is received.
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wait for clk_period;
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INTA_I <= '0'; --send ack in the next clk cycle.
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wait for clk_period;
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INTA_I <= '1'; --reset ack.
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wait for clk_period*20; --ISR takes 20 clk cycles for execution.
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DataBus <= "10100011"; --tell pic that ISR is completed.
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INTA_I <= '0';
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wait for clk_period;
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INTA_I <= '1';
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DataBus <= (others => 'Z');
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--First interrupt executed successfully.
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wait for clk_period*10;
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RST_I <= '1';
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wait for clk_period;
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RST_I <= '0';
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wait for clk_period;
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--set polling method and priority of interrupts.
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--descending order of priority: 7,3,4,5,6,1,2,0;
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DataBus <= "11101110";
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wait for clk_period;
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DataBus <= "10010110";
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wait for clk_period;
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DataBus <= "11000110";
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wait for clk_period;
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DataBus <= "01000010";
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wait for clk_period;
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DataBus <= (others => 'Z'); --make databus as high impedance.
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wait until INTR_O = '1'; --wait for an interrupt.
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wait for clk_period;
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INTA_I <= '0'; --send ack in the next clk cycle.
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wait for clk_period;
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INTA_I <= '1'; --reset ack.
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wait until DataBus = "10011011"; --wait till info abt interrupt is received.
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wait for clk_period;
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INTA_I <= '0'; --send ack in the next clk cycle.
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wait for clk_period;
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INTA_I <= '1'; --reset ack.
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wait for clk_period*20; --ISR takes 20 clk cycles for execution.
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DataBus <= "01100011"; --tell pic that ISR is completed.
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INTA_I <= '0';
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wait for clk_period;
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INTA_I <= '1';
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DataBus <= (others => 'Z');
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wait;
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end process;
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--External interrupts.
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external_ints : process
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begin
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wait for clk_period*15;
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IR(3) <= '1';
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wait until INTA_I='1';
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wait until INTA_I='1';
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IR(3) <= '0';
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wait for clk_period*60;
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IR <= "00101001"; --Interrupts 0,3 and 5.
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wait until INTA_I='1';
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wait until INTA_I='1';
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IR <= (others => '0');
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wait;
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end process;
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END;
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