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[/] [pid_controller/] [trunk/] [RTL/] [16x16bit_multiplier_pipelined.v] - Blame information for rev 2

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Line No. Rev Author Line
1 2 m99 
/*16x16-bit multiplier
2 
Author: Zhu Xu
3 
Email: m99a1@yahoo.cn
4 
*/
5 
 
6 
//Booth Encoder Array
7 
module booth_array(
8 
input   [15:0]multiplier,
9 
output  [7:0]zero,
10 
output  [7:0]double,
11 
output  [7:0]negation
12 
);
13 
 
14 
booth_radix4    booth_radix4_0(
15 
{multiplier[1:0],1'b0},
16 
zero[0],
17 
double[0],
18 
negation[0]
19 
);
20 
 
21 
booth_radix4    booth_radix4_1(
22 
multiplier[3:1],
23 
zero[1],
24 
double[1],
25 
negation[1]
26 
);
27 
 
28 
booth_radix4    booth_radix4_2(
29 
multiplier[5:3],
30 
zero[2],
31 
double[2],
32 
negation[2]
33 
);
34 
booth_radix4    booth_radix4_3(
35 
multiplier[7:5],
36 
zero[3],
37 
double[3],
38 
negation[3]
39 
);
40 
 
41 
booth_radix4    booth_radix4_4(
42 
multiplier[9:7],
43 
zero[4],
44 
double[4],
45 
negation[4]
46 
);
47 
 
48 
booth_radix4    booth_radix4_5(
49 
multiplier[11:9],
50 
zero[5],
51 
double[5],
52 
negation[5]
53 
);
54 
booth_radix4    booth_radix4_6(
55 
multiplier[13:11],
56 
zero[6],
57 
double[6],
58 
negation[6]
59 
);
60 
 
61 
booth_radix4    booth_radix4_7(
62 
multiplier[15:13],
63 
zero[7],
64 
double[7],
65 
negation[7]
66 
);
67 
 
68 
endmodule
69 
 
70 
/*partial product generator unit
71 
generate one 17-bit partial with inversed MSB without correction bit for negation
72 
*/
73 
module partial_product_gen(
74 
input   [15:0]md,                //multiplicand
75 
input   zero,
76 
input   double,
77 
input   negation,
78 
output  [16:0]pp
79 
);
80 
 
81 
wire    [15:0]nmd;
82 
assign  nmd=negation?~md:md;
83 
 
84 
wire    [15:0]zmd;
85 
assign  zmd=zero?0:nmd;
86 
 
87 
assign  pp=double?{~zmd[15],zmd[14:0],negation}:{~zmd[15],zmd[15:0]};
88 
 
89 
endmodule
90 
 
91 
module  half_adder(
92 
input   A,
93 
input   B,
94 
output  S,
95 
output  carry
96 
);
97 
assign  S=A^B;
98 
assign  carry=A&B;
99 
endmodule
100 
 
101 
module full_adder(
102 
input   A,
103 
input   B,
104 
input   cin,
105 
output  S,
106 
output  cout
107 
);
108 
wire    AB;
109 
assign  AB=A&B;
110 
wire    AxorB;
111 
assign  AxorB=A^B;
112 
assign  S=AxorB^cin;
113 
assign  cout=AB|(AxorB&cin);
114 
endmodule
115 
 
116 
module  compressor42(
117 
input   A,
118 
input   B,
119 
input   C,
120 
input   D,
121 
input   cin,
122 
output  S,
123 
output  carry,
124 
output  cout
125 
);
126 
wire    AB;
127 
assign  AB=A&B;
128 
wire    AxorB;
129 
assign  AxorB=A^B;
130 
wire    CD;
131 
assign  CD=C&D;
132 
wire    CxorD;
133 
assign  CxorD=C^D;
134 
 
135 
wire    AxBxCxD=AxorB^CxorD;
136 
 
137 
assign  cout=AB|CD;
138 
assign  carry=(AB&CD)|(AxorB&CxorD)|((AxBxCxD)&cin);
139 
 
140 
assign  S=AxBxCxD^cin;
141 
 
142 
endmodule
143 
 
144 
 
145 
module  multiplier_16x16bit_pipelined(
146 
input   i_clk,
147 
input   i_rst,
148 
input   i_start,
149 
input   [15:0]i_md,
150 
input   [15:0]i_mr,
151 
output  [31:0]o_product,
152 
output  o_ready
153 
);
154 
/////////////////////////////////////////////////////////////stage 0///////////////////////////////////////////////////
155 
 
156 
reg     [15:0]md;
157 
reg     [15:0]mr;
158 
reg     stage_0_ready;
159 
 
160 
always @(posedge i_clk or negedge i_rst)begin
161 
        if(!i_rst)begin
162 
                md<=0;
163 
                mr<=0;
164 
                stage_0_ready<=0;
165 
        end
166 
        else begin
167 
                if(i_start)begin
168 
                        md<=i_md;
169 
                        mr<=i_mr;
170 
                end
171 
                stage_0_ready<=i_start;
172 
        end
173 
 
174 
end
175 
 
176 
wire    [7:0]zero;
177 
wire    [7:0]double;
178 
wire    [7:0]negation;
179 
 
180 
booth_array     booth_array_0(
181 
mr,
182 
zero,
183 
double,
184 
negation
185 
);
186 
 
187 
 
188 
//layer 0
189 
wire    layer_0_w0[1:0];
190 
wire    layer_0_w1;
191 
wire    layer_0_w2[2:0];
192 
wire    layer_0_w3[1:0];
193 
wire    layer_0_w4[3:0];
194 
wire    layer_0_w5[2:0];
195 
wire    layer_0_w6[4:0];
196 
wire    layer_0_w7[3:0];
197 
wire    layer_0_w8[5:0];
198 
wire    layer_0_w9[4:0];
199 
wire    layer_0_w10[6:0];
200 
wire    layer_0_w11[5:0];
201 
wire    layer_0_w12[7:0];
202 
wire    layer_0_w13[6:0];
203 
wire    layer_0_w14[8:0];
204 
wire    layer_0_w15[7:0];
205 
wire    layer_0_w16[8:0];
206 
wire    layer_0_w17[7:0];
207 
wire    layer_0_w18[6:0];
208 
wire    layer_0_w19[6:0];
209 
wire    layer_0_w20[5:0];
210 
wire    layer_0_w21[5:0];
211 
wire    layer_0_w22[4:0];
212 
wire    layer_0_w23[4:0];
213 
wire    layer_0_w24[3:0];
214 
wire    layer_0_w25[3:0];
215 
wire    layer_0_w26[2:0];
216 
wire    layer_0_w27[2:0];
217 
wire    layer_0_w28[1:0];
218 
wire    layer_0_w29[1:0];
219 
wire    layer_0_w30;
220 
wire    layer_0_w31;
221 
partial_product_gen     partial_product_gen_0(
222 
md,
223 
zero[0],
224 
double[0],
225 
negation[0],
226 
{layer_0_w16[0],layer_0_w15[0],layer_0_w14[0],layer_0_w13[0],layer_0_w12[0],layer_0_w11[0],layer_0_w10[0],layer_0_w9[0],layer_0_w8[0],layer_0_w7[0],layer_0_w6[0],layer_0_w5[0],layer_0_w4[0],layer_0_w3[0],layer_0_w2[0],layer_0_w1,layer_0_w0[0]}
227 
);
228 
partial_product_gen     partial_product_gen_1(
229 
md,
230 
zero[1],
231 
double[1],
232 
negation[1],
233 
{layer_0_w18[0],layer_0_w17[0],layer_0_w16[1],layer_0_w15[1],layer_0_w14[1],layer_0_w13[1],layer_0_w12[1],layer_0_w11[1],layer_0_w10[1],layer_0_w9[1],layer_0_w8[1],layer_0_w7[1],layer_0_w6[1],layer_0_w5[1],layer_0_w4[1],layer_0_w3[1],layer_0_w2[1]}
234 
);
235 
partial_product_gen     partial_product_gen_2(
236 
md,
237 
zero[2],
238 
double[2],
239 
negation[2],
240 
{layer_0_w20[0],layer_0_w19[0],layer_0_w18[1],layer_0_w17[1],layer_0_w16[2],layer_0_w15[2],layer_0_w14[2],layer_0_w13[2],layer_0_w12[2],layer_0_w11[2],layer_0_w10[2],layer_0_w9[2],layer_0_w8[2],layer_0_w7[2],layer_0_w6[2],layer_0_w5[2],layer_0_w4[2]}
241 
);
242 
partial_product_gen     partial_product_gen_3(
243 
md,
244 
zero[3],
245 
double[3],
246 
negation[3],
247 
{layer_0_w22[0],layer_0_w21[0],layer_0_w20[1],layer_0_w19[1],layer_0_w18[2],layer_0_w17[2],layer_0_w16[3],layer_0_w15[3],layer_0_w14[3],layer_0_w13[3],layer_0_w12[3],layer_0_w11[3],layer_0_w10[3],layer_0_w9[3],layer_0_w8[3],layer_0_w7[3],layer_0_w6[3]}
248 
);
249 
partial_product_gen     partial_product_gen_4(
250 
md,
251 
zero[4],
252 
double[4],
253 
negation[4],
254 
{layer_0_w24[0],layer_0_w23[0],layer_0_w22[1],layer_0_w21[1],layer_0_w20[2],layer_0_w19[2],layer_0_w18[3],layer_0_w17[3],layer_0_w16[4],layer_0_w15[4],layer_0_w14[4],layer_0_w13[4],layer_0_w12[4],layer_0_w11[4],layer_0_w10[4],layer_0_w9[4],layer_0_w8[4]}
255 
);
256 
partial_product_gen     partial_product_gen_5(
257 
md,
258 
zero[5],
259 
double[5],
260 
negation[5],
261 
{layer_0_w26[0],layer_0_w25[0],layer_0_w24[1],layer_0_w23[1],layer_0_w22[2],layer_0_w21[2],layer_0_w20[3],layer_0_w19[3],layer_0_w18[4],layer_0_w17[4],layer_0_w16[5],layer_0_w15[5],layer_0_w14[5],layer_0_w13[5],layer_0_w12[5],layer_0_w11[5],layer_0_w10[5]}
262 
);
263 
partial_product_gen     partial_product_gen_6(
264 
md,
265 
zero[6],
266 
double[6],
267 
negation[6],
268 
{layer_0_w28[0],layer_0_w27[0],layer_0_w26[1],layer_0_w25[1],layer_0_w24[2],layer_0_w23[2],layer_0_w22[3],layer_0_w21[3],layer_0_w20[4],layer_0_w19[4],layer_0_w18[5],layer_0_w17[5],layer_0_w16[6],layer_0_w15[6],layer_0_w14[6],layer_0_w13[6],layer_0_w12[6]}
269 
);
270 
partial_product_gen     partial_product_gen_7(
271 
md,
272 
zero[7],
273 
double[7],
274 
negation[7],
275 
{layer_0_w30,layer_0_w29[0],layer_0_w28[1],layer_0_w27[1],layer_0_w26[2],layer_0_w25[2],layer_0_w24[3],layer_0_w23[3],layer_0_w22[4],layer_0_w21[4],layer_0_w20[5],layer_0_w19[5],layer_0_w18[6],layer_0_w17[6],layer_0_w16[7],layer_0_w15[7],layer_0_w14[7]}
276 
);
277 
//correction for negation
278 
assign  layer_0_w0[1]=negation[0];
279 
//sign extension
280 
assign  layer_0_w16[8]=1;
281 
assign  layer_0_w17[7]=1;
282 
//correction for negation
283 
assign  layer_0_w2[2]=negation[1];
284 
//sign extension
285 
assign  layer_0_w19[6]=1;
286 
//correction for negation
287 
assign  layer_0_w4[3]=negation[2];
288 
//sign extension
289 
assign  layer_0_w21[5]=1;
290 
//correction for negation
291 
assign  layer_0_w6[4]=negation[3];
292 
//sign extension
293 
assign  layer_0_w23[4]=1;
294 
//correction for negation
295 
assign  layer_0_w8[5]=negation[4];
296 
//sign extension
297 
assign  layer_0_w25[3]=1;
298 
//correction for negation
299 
assign  layer_0_w10[6]=negation[5];
300 
//sign extension
301 
assign  layer_0_w27[2]=1;
302 
//correction for negation
303 
assign  layer_0_w12[7]=negation[6];
304 
//sign extension
305 
assign  layer_0_w29[1]=1;
306 
//correction for negation
307 
assign  layer_0_w14[8]=negation[7];
308 
//sign extension
309 
assign  layer_0_w31=1;
310 
 
311 
//layer 1
312 
wire    layer_1_w0[1:0];
313 
wire    layer_1_w1;
314 
wire    layer_1_w2[2:0];
315 
wire    layer_1_w3[1:0];
316 
wire    layer_1_w4[1:0];
317 
wire    layer_1_w5[1:0];
318 
wire    layer_1_w6[1:0];
319 
wire    layer_1_w7[3:0];
320 
wire    layer_1_w8[2:0];
321 
wire    layer_1_w9[2:0];
322 
wire    layer_1_w10[4:0];
323 
wire    layer_1_w11[3:0];
324 
wire    layer_1_w12[3:0];
325 
wire    layer_1_w13[5:0];
326 
wire    layer_1_w14[4:0];
327 
wire    layer_1_w15[4:0];
328 
wire    layer_1_w16[5:0];
329 
wire    layer_1_w17[4:0];
330 
wire    layer_1_w18[5:0];
331 
wire    layer_1_w19[4:0];
332 
wire    layer_1_w20[3:0];
333 
wire    layer_1_w21[3:0];
334 
wire    layer_1_w22[2:0];
335 
wire    layer_1_w23[2:0];
336 
wire    layer_1_w24[3:0];
337 
wire    layer_1_w25[2:0];
338 
wire    layer_1_w26[1:0];
339 
wire    layer_1_w27[1:0];
340 
wire    layer_1_w28[2:0];
341 
wire    layer_1_w29[1:0];
342 
wire    layer_1_w30;
343 
wire    layer_1_w31;
344 
assign  layer_1_w0[0]=layer_0_w0[0];
345 
assign  layer_1_w0[1]=layer_0_w0[1];
346 
assign  layer_1_w1=layer_0_w1;
347 
assign  layer_1_w2[0]=layer_0_w2[0];
348 
assign  layer_1_w2[1]=layer_0_w2[1];
349 
assign  layer_1_w2[2]=layer_0_w2[2];
350 
assign  layer_1_w3[0]=layer_0_w3[0];
351 
assign  layer_1_w3[1]=layer_0_w3[1];
352 
full_adder      layer_1_full_adder_0(
353 
layer_0_w4[0],
354 
layer_0_w4[1],
355 
layer_0_w4[2],
356 
layer_1_w4[0],
357 
layer_1_w5[0]
358 
);
359 
assign  layer_1_w4[1]=layer_0_w4[3];
360 
full_adder      layer_1_full_adder_1(
361 
layer_0_w5[0],
362 
layer_0_w5[1],
363 
layer_0_w5[2],
364 
layer_1_w5[1],
365 
layer_1_w6[0]
366 
);
367 
compressor42    layer_1_compressor42_0(
368 
layer_0_w6[0],
369 
layer_0_w6[1],
370 
layer_0_w6[2],
371 
layer_0_w6[3],
372 
layer_0_w6[4],
373 
layer_1_w6[1],
374 
layer_1_w7[0],
375 
layer_1_w7[1]
376 
);
377 
full_adder      layer_1_full_adder_2(
378 
layer_0_w7[0],
379 
layer_0_w7[1],
380 
layer_0_w7[2],
381 
layer_1_w7[2],
382 
layer_1_w8[0]
383 
);
384 
assign  layer_1_w7[3]=layer_0_w7[3];
385 
compressor42    layer_1_compressor42_1(
386 
layer_0_w8[0],
387 
layer_0_w8[1],
388 
layer_0_w8[2],
389 
layer_0_w8[3],
390 
layer_0_w8[4],
391 
layer_1_w8[1],
392 
layer_1_w9[0],
393 
layer_1_w9[1]
394 
);
395 
assign  layer_1_w8[2]=layer_0_w8[5];
396 
compressor42    layer_1_compressor42_2(
397 
layer_0_w9[0],
398 
layer_0_w9[1],
399 
layer_0_w9[2],
400 
layer_0_w9[3],
401 
layer_0_w9[4],
402 
layer_1_w9[2],
403 
layer_1_w10[0],
404 
layer_1_w10[1]
405 
);
406 
compressor42    layer_1_compressor42_3(
407 
layer_0_w10[0],
408 
layer_0_w10[1],
409 
layer_0_w10[2],
410 
layer_0_w10[3],
411 
layer_0_w10[4],
412 
layer_1_w10[2],
413 
layer_1_w11[0],
414 
layer_1_w11[1]
415 
);
416 
assign  layer_1_w10[3]=layer_0_w10[5];
417 
assign  layer_1_w10[4]=layer_0_w10[6];
418 
compressor42    layer_1_compressor42_4(
419 
layer_0_w11[0],
420 
layer_0_w11[1],
421 
layer_0_w11[2],
422 
layer_0_w11[3],
423 
layer_0_w11[4],
424 
layer_1_w11[2],
425 
layer_1_w12[0],
426 
layer_1_w12[1]
427 
);
428 
assign  layer_1_w11[3]=layer_0_w11[5];
429 
compressor42    layer_1_compressor42_5(
430 
layer_0_w12[0],
431 
layer_0_w12[1],
432 
layer_0_w12[2],
433 
layer_0_w12[3],
434 
layer_0_w12[4],
435 
layer_1_w12[2],
436 
layer_1_w13[0],
437 
layer_1_w13[1]
438 
);
439 
full_adder      layer_1_full_adder_3(
440 
layer_0_w12[5],
441 
layer_0_w12[6],
442 
layer_0_w12[7],
443 
layer_1_w12[3],
444 
layer_1_w13[2]
445 
);
446 
compressor42    layer_1_compressor42_6(
447 
layer_0_w13[0],
448 
layer_0_w13[1],
449 
layer_0_w13[2],
450 
layer_0_w13[3],
451 
layer_0_w13[4],
452 
layer_1_w13[3],
453 
layer_1_w14[0],
454 
layer_1_w14[1]
455 
);
456 
assign  layer_1_w13[4]=layer_0_w13[5];
457 
assign  layer_1_w13[5]=layer_0_w13[6];
458 
compressor42    layer_1_compressor42_7(
459 
layer_0_w14[0],
460 
layer_0_w14[1],
461 
layer_0_w14[2],
462 
layer_0_w14[3],
463 
layer_0_w14[4],
464 
layer_1_w14[2],
465 
layer_1_w15[0],
466 
layer_1_w15[1]
467 
);
468 
full_adder      layer_1_full_adder_4(
469 
layer_0_w14[5],
470 
layer_0_w14[6],
471 
layer_0_w14[7],
472 
layer_1_w14[3],
473 
layer_1_w15[2]
474 
);
475 
assign  layer_1_w14[4]=layer_0_w14[8];
476 
compressor42    layer_1_compressor42_8(
477 
layer_0_w15[0],
478 
layer_0_w15[1],
479 
layer_0_w15[2],
480 
layer_0_w15[3],
481 
layer_0_w15[4],
482 
layer_1_w15[3],
483 
layer_1_w16[0],
484 
layer_1_w16[1]
485 
);
486 
full_adder      layer_1_full_adder_5(
487 
layer_0_w15[5],
488 
layer_0_w15[6],
489 
layer_0_w15[7],
490 
layer_1_w15[4],
491 
layer_1_w16[2]
492 
);
493 
compressor42    layer_1_compressor42_9(
494 
layer_0_w16[0],
495 
layer_0_w16[1],
496 
layer_0_w16[2],
497 
layer_0_w16[3],
498 
layer_0_w16[4],
499 
layer_1_w16[3],
500 
layer_1_w17[0],
501 
layer_1_w17[1]
502 
);
503 
full_adder      layer_1_full_adder_6(
504 
layer_0_w16[5],
505 
layer_0_w16[6],
506 
layer_0_w16[7],
507 
layer_1_w16[4],
508 
layer_1_w17[2]
509 
);
510 
assign  layer_1_w16[5]=layer_0_w16[8];
511 
compressor42    layer_1_compressor42_10(
512 
layer_0_w17[0],
513 
layer_0_w17[1],
514 
layer_0_w17[2],
515 
layer_0_w17[3],
516 
layer_0_w17[4],
517 
layer_1_w17[3],
518 
layer_1_w18[0],
519 
layer_1_w18[1]
520 
);
521 
full_adder      layer_1_full_adder_7(
522 
layer_0_w17[5],
523 
layer_0_w17[6],
524 
layer_0_w17[7],
525 
layer_1_w17[4],
526 
layer_1_w18[2]
527 
);
528 
compressor42    layer_1_compressor42_11(
529 
layer_0_w18[0],
530 
layer_0_w18[1],
531 
layer_0_w18[2],
532 
layer_0_w18[3],
533 
layer_0_w18[4],
534 
layer_1_w18[3],
535 
layer_1_w19[0],
536 
layer_1_w19[1]
537 
);
538 
assign  layer_1_w18[4]=layer_0_w18[5];
539 
assign  layer_1_w18[5]=layer_0_w18[6];
540 
compressor42    layer_1_compressor42_12(
541 
layer_0_w19[0],
542 
layer_0_w19[1],
543 
layer_0_w19[2],
544 
layer_0_w19[3],
545 
layer_0_w19[4],
546 
layer_1_w19[2],
547 
layer_1_w20[0],
548 
layer_1_w20[1]
549 
);
550 
assign  layer_1_w19[3]=layer_0_w19[5];
551 
assign  layer_1_w19[4]=layer_0_w19[6];
552 
compressor42    layer_1_compressor42_13(
553 
layer_0_w20[0],
554 
layer_0_w20[1],
555 
layer_0_w20[2],
556 
layer_0_w20[3],
557 
layer_0_w20[4],
558 
layer_1_w20[2],
559 
layer_1_w21[0],
560 
layer_1_w21[1]
561 
);
562 
assign  layer_1_w20[3]=layer_0_w20[5];
563 
compressor42    layer_1_compressor42_14(
564 
layer_0_w21[0],
565 
layer_0_w21[1],
566 
layer_0_w21[2],
567 
layer_0_w21[3],
568 
layer_0_w21[4],
569 
layer_1_w21[2],
570 
layer_1_w22[0],
571 
layer_1_w22[1]
572 
);
573 
assign  layer_1_w21[3]=layer_0_w21[5];
574 
compressor42    layer_1_compressor42_15(
575 
layer_0_w22[0],
576 
layer_0_w22[1],
577 
layer_0_w22[2],
578 
layer_0_w22[3],
579 
layer_0_w22[4],
580 
layer_1_w22[2],
581 
layer_1_w23[0],
582 
layer_1_w23[1]
583 
);
584 
compressor42    layer_1_compressor42_16(
585 
layer_0_w23[0],
586 
layer_0_w23[1],
587 
layer_0_w23[2],
588 
layer_0_w23[3],
589 
layer_0_w23[4],
590 
layer_1_w23[2],
591 
layer_1_w24[0],
592 
layer_1_w24[1]
593 
);
594 
full_adder      layer_1_full_adder_8(
595 
layer_0_w24[0],
596 
layer_0_w24[1],
597 
layer_0_w24[2],
598 
layer_1_w24[2],
599 
layer_1_w25[0]
600 
);
601 
assign  layer_1_w24[3]=layer_0_w24[3];
602 
full_adder      layer_1_full_adder_9(
603 
layer_0_w25[0],
604 
layer_0_w25[1],
605 
layer_0_w25[2],
606 
layer_1_w25[1],
607 
layer_1_w26[0]
608 
);
609 
assign  layer_1_w25[2]=layer_0_w25[3];
610 
full_adder      layer_1_full_adder_10(
611 
layer_0_w26[0],
612 
layer_0_w26[1],
613 
layer_0_w26[2],
614 
layer_1_w26[1],
615 
layer_1_w27[0]
616 
);
617 
full_adder      layer_1_full_adder_11(
618 
layer_0_w27[0],
619 
layer_0_w27[1],
620 
layer_0_w27[2],
621 
layer_1_w27[1],
622 
layer_1_w28[0]
623 
);
624 
assign  layer_1_w28[1]=layer_0_w28[0];
625 
assign  layer_1_w28[2]=layer_0_w28[1];
626 
assign  layer_1_w29[0]=layer_0_w29[0];
627 
assign  layer_1_w29[1]=layer_0_w29[1];
628 
assign  layer_1_w30=layer_0_w30;
629 
assign  layer_1_w31=layer_0_w31;
630 
 
631 
//layer 2
632 
wire    [1:0]layer_2_w0;
633 
wire    layer_2_w1;
634 
wire    [2:0]layer_2_w2;
635 
wire    [1:0]layer_2_w3;
636 
wire    [1:0]layer_2_w4;
637 
wire    [1:0]layer_2_w5;
638 
wire    [1:0]layer_2_w6;
639 
wire    [1:0]layer_2_w7;
640 
wire    [1:0]layer_2_w8;
641 
wire    [1:0]layer_2_w9;
642 
wire    [1:0]layer_2_w10;
643 
wire    [3:0]layer_2_w11;
644 
wire    [2:0]layer_2_w12;
645 
wire    [2:0]layer_2_w13;
646 
wire    [2:0]layer_2_w14;
647 
wire    [2:0]layer_2_w15;
648 
wire    [3:0]layer_2_w16;
649 
wire    [2:0]layer_2_w17;
650 
wire    [3:0]layer_2_w18;
651 
wire    [2:0]layer_2_w19;
652 
wire    [3:0]layer_2_w20;
653 
wire    [2:0]layer_2_w21;
654 
wire    [1:0]layer_2_w22;
655 
wire    [1:0]layer_2_w23;
656 
wire    [2:0]layer_2_w24;
657 
wire    [1:0]layer_2_w25;
658 
wire    [2:0]layer_2_w26;
659 
wire    [1:0]layer_2_w27;
660 
wire    layer_2_w28;
661 
wire    [2:0]layer_2_w29;
662 
wire    layer_2_w30;
663 
wire    layer_2_w31;
664 
assign  layer_2_w0[0]=layer_1_w0[0];
665 
assign  layer_2_w0[1]=layer_1_w0[1];
666 
assign  layer_2_w1=layer_1_w1;
667 
assign  layer_2_w2[0]=layer_1_w2[0];
668 
assign  layer_2_w2[1]=layer_1_w2[1];
669 
assign  layer_2_w2[2]=layer_1_w2[2];
670 
assign  layer_2_w3[0]=layer_1_w3[0];
671 
assign  layer_2_w3[1]=layer_1_w3[1];
672 
assign  layer_2_w4[0]=layer_1_w4[0];
673 
assign  layer_2_w4[1]=layer_1_w4[1];
674 
assign  layer_2_w5[0]=layer_1_w5[0];
675 
assign  layer_2_w5[1]=layer_1_w5[1];
676 
assign  layer_2_w6[0]=layer_1_w6[0];
677 
assign  layer_2_w6[1]=layer_1_w6[1];
678 
full_adder      layer_2_full_adder_0(
679 
layer_1_w7[0],
680 
layer_1_w7[1],
681 
layer_1_w7[2],
682 
layer_2_w7[0],
683 
layer_2_w8[0]
684 
);
685 
assign  layer_2_w7[1]=layer_1_w7[3];
686 
full_adder      layer_2_full_adder_1(
687 
layer_1_w8[0],
688 
layer_1_w8[1],
689 
layer_1_w8[2],
690 
layer_2_w8[1],
691 
layer_2_w9[0]
692 
);
693 
full_adder      layer_2_full_adder_2(
694 
layer_1_w9[0],
695 
layer_1_w9[1],
696 
layer_1_w9[2],
697 
layer_2_w9[1],
698 
layer_2_w10[0]
699 
);
700 
compressor42    layer_2_compressor42_0(
701 
layer_1_w10[0],
702 
layer_1_w10[1],
703 
layer_1_w10[2],
704 
layer_1_w10[3],
705 
layer_1_w10[4],
706 
layer_2_w10[1],
707 
layer_2_w11[0],
708 
layer_2_w11[1]
709 
);
710 
full_adder      layer_2_full_adder_3(
711 
layer_1_w11[0],
712 
layer_1_w11[1],
713 
layer_1_w11[2],
714 
layer_2_w11[2],
715 
layer_2_w12[0]
716 
);
717 
assign  layer_2_w11[3]=layer_1_w11[3];
718 
full_adder      layer_2_full_adder_4(
719 
layer_1_w12[0],
720 
layer_1_w12[1],
721 
layer_1_w12[2],
722 
layer_2_w12[1],
723 
layer_2_w13[0]
724 
);
725 
assign  layer_2_w12[2]=layer_1_w12[3];
726 
compressor42    layer_2_compressor42_1(
727 
layer_1_w13[0],
728 
layer_1_w13[1],
729 
layer_1_w13[2],
730 
layer_1_w13[3],
731 
layer_1_w13[4],
732 
layer_2_w13[1],
733 
layer_2_w14[0],
734 
layer_2_w14[1]
735 
);
736 
assign  layer_2_w13[2]=layer_1_w13[5];
737 
compressor42    layer_2_compressor42_2(
738 
layer_1_w14[0],
739 
layer_1_w14[1],
740 
layer_1_w14[2],
741 
layer_1_w14[3],
742 
layer_1_w14[4],
743 
layer_2_w14[2],
744 
layer_2_w15[0],
745 
layer_2_w15[1]
746 
);
747 
compressor42    layer_2_compressor42_3(
748 
layer_1_w15[0],
749 
layer_1_w15[1],
750 
layer_1_w15[2],
751 
layer_1_w15[3],
752 
layer_1_w15[4],
753 
layer_2_w15[2],
754 
layer_2_w16[0],
755 
layer_2_w16[1]
756 
);
757 
compressor42    layer_2_compressor42_4(
758 
layer_1_w16[0],
759 
layer_1_w16[1],
760 
layer_1_w16[2],
761 
layer_1_w16[3],
762 
layer_1_w16[4],
763 
layer_2_w16[2],
764 
layer_2_w17[0],
765 
layer_2_w17[1]
766 
);
767 
assign  layer_2_w16[3]=layer_1_w16[5];
768 
compressor42    layer_2_compressor42_5(
769 
layer_1_w17[0],
770 
layer_1_w17[1],
771 
layer_1_w17[2],
772 
layer_1_w17[3],
773 
layer_1_w17[4],
774 
layer_2_w17[2],
775 
layer_2_w18[0],
776 
layer_2_w18[1]
777 
);
778 
compressor42    layer_2_compressor42_6(
779 
layer_1_w18[0],
780 
layer_1_w18[1],
781 
layer_1_w18[2],
782 
layer_1_w18[3],
783 
layer_1_w18[4],
784 
layer_2_w18[2],
785 
layer_2_w19[0],
786 
layer_2_w19[1]
787 
);
788 
assign  layer_2_w18[3]=layer_1_w18[5];
789 
compressor42    layer_2_compressor42_7(
790 
layer_1_w19[0],
791 
layer_1_w19[1],
792 
layer_1_w19[2],
793 
layer_1_w19[3],
794 
layer_1_w19[4],
795 
layer_2_w19[2],
796 
layer_2_w20[0],
797 
layer_2_w20[1]
798 
);
799 
full_adder      layer_2_full_adder_5(
800 
layer_1_w20[0],
801 
layer_1_w20[1],
802 
layer_1_w20[2],
803 
layer_2_w20[2],
804 
layer_2_w21[0]
805 
);
806 
assign  layer_2_w20[3]=layer_1_w20[3];
807 
full_adder      layer_2_full_adder_6(
808 
layer_1_w21[0],
809 
layer_1_w21[1],
810 
layer_1_w21[2],
811 
layer_2_w21[1],
812 
layer_2_w22[0]
813 
);
814 
assign  layer_2_w21[2]=layer_1_w21[3];
815 
full_adder      layer_2_full_adder_7(
816 
layer_1_w22[0],
817 
layer_1_w22[1],
818 
layer_1_w22[2],
819 
layer_2_w22[1],
820 
layer_2_w23[0]
821 
);
822 
full_adder      layer_2_full_adder_8(
823 
layer_1_w23[0],
824 
layer_1_w23[1],
825 
layer_1_w23[2],
826 
layer_2_w23[1],
827 
layer_2_w24[0]
828 
);
829 
full_adder      layer_2_full_adder_9(
830 
layer_1_w24[0],
831 
layer_1_w24[1],
832 
layer_1_w24[2],
833 
layer_2_w24[1],
834 
layer_2_w25[0]
835 
);
836 
assign  layer_2_w24[2]=layer_1_w24[3];
837 
full_adder      layer_2_full_adder_10(
838 
layer_1_w25[0],
839 
layer_1_w25[1],
840 
layer_1_w25[2],
841 
layer_2_w25[1],
842 
layer_2_w26[0]
843 
);
844 
assign  layer_2_w26[1]=layer_1_w26[0];
845 
assign  layer_2_w26[2]=layer_1_w26[1];
846 
assign  layer_2_w27[0]=layer_1_w27[0];
847 
assign  layer_2_w27[1]=layer_1_w27[1];
848 
full_adder      layer_2_full_adder_11(
849 
layer_1_w28[0],
850 
layer_1_w28[1],
851 
layer_1_w28[2],
852 
layer_2_w28,
853 
layer_2_w29[0]
854 
);
855 
assign  layer_2_w29[1]=layer_1_w29[0];
856 
assign  layer_2_w29[2]=layer_1_w29[1];
857 
assign  layer_2_w30=layer_1_w30;
858 
assign  layer_2_w31=layer_1_w31;
859 
 
860 
 
861 
///////////////////////////////////////////////////////stage 1///////////////////////////////////////////////////////
862 
reg     [1:0]reg_layer_2_w0;
863 
reg     reg_layer_2_w1;
864 
reg     [2:0]reg_layer_2_w2;
865 
reg     [1:0]reg_layer_2_w3;
866 
reg     [1:0]reg_layer_2_w4;
867 
reg     [1:0]reg_layer_2_w5;
868 
reg     [1:0]reg_layer_2_w6;
869 
reg     [1:0]reg_layer_2_w7;
870 
reg     [1:0]reg_layer_2_w8;
871 
reg     [1:0]reg_layer_2_w9;
872 
reg     [1:0]reg_layer_2_w10;
873 
reg     [3:0]reg_layer_2_w11;
874 
reg     [2:0]reg_layer_2_w12;
875 
reg     [2:0]reg_layer_2_w13;
876 
reg     [2:0]reg_layer_2_w14;
877 
reg     [2:0]reg_layer_2_w15;
878 
reg     [3:0]reg_layer_2_w16;
879 
reg     [2:0]reg_layer_2_w17;
880 
reg     [3:0]reg_layer_2_w18;
881 
reg     [2:0]reg_layer_2_w19;
882 
reg     [3:0]reg_layer_2_w20;
883 
reg     [2:0]reg_layer_2_w21;
884 
reg     [1:0]reg_layer_2_w22;
885 
reg     [1:0]reg_layer_2_w23;
886 
reg     [2:0]reg_layer_2_w24;
887 
reg     [1:0]reg_layer_2_w25;
888 
reg     [2:0]reg_layer_2_w26;
889 
reg     [1:0]reg_layer_2_w27;
890 
reg     reg_layer_2_w28;
891 
reg     [2:0]reg_layer_2_w29;
892 
reg     reg_layer_2_w30;
893 
reg     reg_layer_2_w31;
894 
reg     stage_1_ready;
895 
assign  o_ready=stage_1_ready;
896 
 
897 
always @(posedge i_clk or negedge i_rst)begin
898 
        if(!i_rst)begin
899 
                stage_1_ready<=0;
900 
                reg_layer_2_w0<=0;
901 
                reg_layer_2_w1<=0;
902 
                reg_layer_2_w2<=0;
903 
                reg_layer_2_w3<=0;
904 
                reg_layer_2_w4<=0;
905 
                reg_layer_2_w5<=0;
906 
                reg_layer_2_w6<=0;
907 
                reg_layer_2_w7<=0;
908 
                reg_layer_2_w8<=0;
909 
                reg_layer_2_w9<=0;
910 
                reg_layer_2_w10<=0;
911 
                reg_layer_2_w11<=0;
912 
                reg_layer_2_w12<=0;
913 
                reg_layer_2_w13<=0;
914 
                reg_layer_2_w14<=0;
915 
                reg_layer_2_w15<=0;
916 
                reg_layer_2_w16<=0;
917 
                reg_layer_2_w17<=0;
918 
                reg_layer_2_w18<=0;
919 
                reg_layer_2_w19<=0;
920 
                reg_layer_2_w20<=0;
921 
                reg_layer_2_w21<=0;
922 
                reg_layer_2_w22<=0;
923 
                reg_layer_2_w23<=0;
924 
                reg_layer_2_w24<=0;
925 
                reg_layer_2_w25<=0;
926 
                reg_layer_2_w26<=0;
927 
                reg_layer_2_w27<=0;
928 
                reg_layer_2_w28<=0;
929 
                reg_layer_2_w29<=0;
930 
                reg_layer_2_w30<=0;
931 
                reg_layer_2_w31<=0;
932 
        end
933 
        else begin
934 
                if(stage_0_ready)begin
935 
                        reg_layer_2_w0<=layer_2_w0;
936 
                        reg_layer_2_w1<=layer_2_w1;
937 
                        reg_layer_2_w2<=layer_2_w2;
938 
                        reg_layer_2_w3<=layer_2_w3;
939 
                        reg_layer_2_w4<=layer_2_w4;
940 
                        reg_layer_2_w5<=layer_2_w5;
941 
                        reg_layer_2_w6<=layer_2_w6;
942 
                        reg_layer_2_w7<=layer_2_w7;
943 
                        reg_layer_2_w8<=layer_2_w8;
944 
                        reg_layer_2_w9<=layer_2_w9;
945 
                        reg_layer_2_w10<=layer_2_w10;
946 
                        reg_layer_2_w11<=layer_2_w11;
947 
                        reg_layer_2_w12<=layer_2_w12;
948 
                        reg_layer_2_w13<=layer_2_w13;
949 
                        reg_layer_2_w14<=layer_2_w14;
950 
                        reg_layer_2_w15<=layer_2_w15;
951 
                        reg_layer_2_w16<=layer_2_w16;
952 
                        reg_layer_2_w17<=layer_2_w17;
953 
                        reg_layer_2_w18<=layer_2_w18;
954 
                        reg_layer_2_w19<=layer_2_w19;
955 
                        reg_layer_2_w20<=layer_2_w20;
956 
                        reg_layer_2_w21<=layer_2_w21;
957 
                        reg_layer_2_w22<=layer_2_w22;
958 
                        reg_layer_2_w23<=layer_2_w23;
959 
                        reg_layer_2_w24<=layer_2_w24;
960 
                        reg_layer_2_w25<=layer_2_w25;
961 
                        reg_layer_2_w26<=layer_2_w26;
962 
                        reg_layer_2_w27<=layer_2_w27;
963 
                        reg_layer_2_w28<=layer_2_w28;
964 
                        reg_layer_2_w29<=layer_2_w29;
965 
                        reg_layer_2_w30<=layer_2_w30;
966 
                        reg_layer_2_w31<=layer_2_w31;
967 
                end
968 
                stage_1_ready<=stage_0_ready;
969 
        end
970 
end
971 
 
972 
//layer 3
973 
wire    layer_3_w0[1:0];
974 
wire    layer_3_w1;
975 
wire    layer_3_w2[2:0];
976 
wire    layer_3_w3[1:0];
977 
wire    layer_3_w4[1:0];
978 
wire    layer_3_w5[1:0];
979 
wire    layer_3_w6[1:0];
980 
wire    layer_3_w7[1:0];
981 
wire    layer_3_w8[1:0];
982 
wire    layer_3_w9[1:0];
983 
wire    layer_3_w10[1:0];
984 
wire    layer_3_w11[1:0];
985 
wire    layer_3_w12[1:0];
986 
wire    layer_3_w13[1:0];
987 
wire    layer_3_w14[1:0];
988 
wire    layer_3_w15[1:0];
989 
wire    layer_3_w16[2:0];
990 
wire    layer_3_w17[1:0];
991 
wire    layer_3_w18[2:0];
992 
wire    layer_3_w19[1:0];
993 
wire    layer_3_w20[2:0];
994 
wire    layer_3_w21[1:0];
995 
wire    layer_3_w22[2:0];
996 
wire    layer_3_w23[1:0];
997 
wire    layer_3_w24;
998 
wire    layer_3_w25[2:0];
999 
wire    layer_3_w26;
1000 
wire    layer_3_w27[2:0];
1001 
wire    layer_3_w28;
1002 
wire    layer_3_w29;
1003 
wire    layer_3_w30[1:0];
1004 
wire    layer_3_w31;
1005 
assign  layer_3_w0[0]=reg_layer_2_w0[0];
1006 
assign  layer_3_w0[1]=reg_layer_2_w0[1];
1007 
assign  layer_3_w1=reg_layer_2_w1;
1008 
assign  layer_3_w2[0]=reg_layer_2_w2[0];
1009 
assign  layer_3_w2[1]=reg_layer_2_w2[1];
1010 
assign  layer_3_w2[2]=reg_layer_2_w2[2];
1011 
assign  layer_3_w3[0]=reg_layer_2_w3[0];
1012 
assign  layer_3_w3[1]=reg_layer_2_w3[1];
1013 
assign  layer_3_w4[0]=reg_layer_2_w4[0];
1014 
assign  layer_3_w4[1]=reg_layer_2_w4[1];
1015 
assign  layer_3_w5[0]=reg_layer_2_w5[0];
1016 
assign  layer_3_w5[1]=reg_layer_2_w5[1];
1017 
assign  layer_3_w6[0]=reg_layer_2_w6[0];
1018 
assign  layer_3_w6[1]=reg_layer_2_w6[1];
1019 
assign  layer_3_w7[0]=reg_layer_2_w7[0];
1020 
assign  layer_3_w7[1]=reg_layer_2_w7[1];
1021 
assign  layer_3_w8[0]=reg_layer_2_w8[0];
1022 
assign  layer_3_w8[1]=reg_layer_2_w8[1];
1023 
assign  layer_3_w9[0]=reg_layer_2_w9[0];
1024 
assign  layer_3_w9[1]=reg_layer_2_w9[1];
1025 
assign  layer_3_w10[0]=reg_layer_2_w10[0];
1026 
assign  layer_3_w10[1]=reg_layer_2_w10[1];
1027 
full_adder      layer_3_full_adder_0(
1028 
reg_layer_2_w11[0],
1029 
reg_layer_2_w11[1],
1030 
reg_layer_2_w11[2],
1031 
layer_3_w11[0],
1032 
layer_3_w12[0]
1033 
);
1034 
assign  layer_3_w11[1]=reg_layer_2_w11[3];
1035 
full_adder      layer_3_full_adder_1(
1036 
reg_layer_2_w12[0],
1037 
reg_layer_2_w12[1],
1038 
reg_layer_2_w12[2],
1039 
layer_3_w12[1],
1040 
layer_3_w13[0]
1041 
);
1042 
full_adder      layer_3_full_adder_2(
1043 
reg_layer_2_w13[0],
1044 
reg_layer_2_w13[1],
1045 
reg_layer_2_w13[2],
1046 
layer_3_w13[1],
1047 
layer_3_w14[0]
1048 
);
1049 
full_adder      layer_3_full_adder_3(
1050 
reg_layer_2_w14[0],
1051 
reg_layer_2_w14[1],
1052 
reg_layer_2_w14[2],
1053 
layer_3_w14[1],
1054 
layer_3_w15[0]
1055 
);
1056 
full_adder      layer_3_full_adder_4(
1057 
reg_layer_2_w15[0],
1058 
reg_layer_2_w15[1],
1059 
reg_layer_2_w15[2],
1060 
layer_3_w15[1],
1061 
layer_3_w16[0]
1062 
);
1063 
full_adder      layer_3_full_adder_5(
1064 
reg_layer_2_w16[0],
1065 
reg_layer_2_w16[1],
1066 
reg_layer_2_w16[2],
1067 
layer_3_w16[1],
1068 
layer_3_w17[0]
1069 
);
1070 
assign  layer_3_w16[2]=reg_layer_2_w16[3];
1071 
full_adder      layer_3_full_adder_6(
1072 
reg_layer_2_w17[0],
1073 
reg_layer_2_w17[1],
1074 
reg_layer_2_w17[2],
1075 
layer_3_w17[1],
1076 
layer_3_w18[0]
1077 
);
1078 
full_adder      layer_3_full_adder_7(
1079 
reg_layer_2_w18[0],
1080 
reg_layer_2_w18[1],
1081 
reg_layer_2_w18[2],
1082 
layer_3_w18[1],
1083 
layer_3_w19[0]
1084 
);
1085 
assign  layer_3_w18[2]=reg_layer_2_w18[3];
1086 
full_adder      layer_3_full_adder_8(
1087 
reg_layer_2_w19[0],
1088 
reg_layer_2_w19[1],
1089 
reg_layer_2_w19[2],
1090 
layer_3_w19[1],
1091 
layer_3_w20[0]
1092 
);
1093 
full_adder      layer_3_full_adder_9(
1094 
reg_layer_2_w20[0],
1095 
reg_layer_2_w20[1],
1096 
reg_layer_2_w20[2],
1097 
layer_3_w20[1],
1098 
layer_3_w21[0]
1099 
);
1100 
assign  layer_3_w20[2]=reg_layer_2_w20[3];
1101 
full_adder      layer_3_full_adder_10(
1102 
reg_layer_2_w21[0],
1103 
reg_layer_2_w21[1],
1104 
reg_layer_2_w21[2],
1105 
layer_3_w21[1],
1106 
layer_3_w22[0]
1107 
);
1108 
assign  layer_3_w22[1]=reg_layer_2_w22[0];
1109 
assign  layer_3_w22[2]=reg_layer_2_w22[1];
1110 
assign  layer_3_w23[0]=reg_layer_2_w23[0];
1111 
assign  layer_3_w23[1]=reg_layer_2_w23[1];
1112 
full_adder      layer_3_full_adder_11(
1113 
reg_layer_2_w24[0],
1114 
reg_layer_2_w24[1],
1115 
reg_layer_2_w24[2],
1116 
layer_3_w24,
1117 
layer_3_w25[0]
1118 
);
1119 
assign  layer_3_w25[1]=reg_layer_2_w25[0];
1120 
assign  layer_3_w25[2]=reg_layer_2_w25[1];
1121 
full_adder      layer_3_full_adder_12(
1122 
reg_layer_2_w26[0],
1123 
reg_layer_2_w26[1],
1124 
reg_layer_2_w26[2],
1125 
layer_3_w26,
1126 
layer_3_w27[0]
1127 
);
1128 
assign  layer_3_w27[1]=reg_layer_2_w27[0];
1129 
assign  layer_3_w27[2]=reg_layer_2_w27[1];
1130 
assign  layer_3_w28=reg_layer_2_w28;
1131 
full_adder      layer_3_full_adder_13(
1132 
reg_layer_2_w29[0],
1133 
reg_layer_2_w29[1],
1134 
reg_layer_2_w29[2],
1135 
layer_3_w29,
1136 
layer_3_w30[0]
1137 
);
1138 
assign  layer_3_w30[1]=reg_layer_2_w30;
1139 
assign  layer_3_w31=reg_layer_2_w31;
1140 
 
1141 
//layer 4
1142 
wire    layer_4_w0[1:0];
1143 
wire    layer_4_w1;
1144 
wire    layer_4_w2;
1145 
wire    layer_4_w3[1:0];
1146 
wire    layer_4_w4[1:0];
1147 
wire    layer_4_w5[1:0];
1148 
wire    layer_4_w6[1:0];
1149 
wire    layer_4_w7[1:0];
1150 
wire    layer_4_w8[1:0];
1151 
wire    layer_4_w9[1:0];
1152 
wire    layer_4_w10[1:0];
1153 
wire    layer_4_w11[1:0];
1154 
wire    layer_4_w12[1:0];
1155 
wire    layer_4_w13[1:0];
1156 
wire    layer_4_w14[1:0];
1157 
wire    layer_4_w15[1:0];
1158 
wire    layer_4_w16[1:0];
1159 
wire    layer_4_w17[1:0];
1160 
wire    layer_4_w18[1:0];
1161 
wire    layer_4_w19[1:0];
1162 
wire    layer_4_w20[1:0];
1163 
wire    layer_4_w21[1:0];
1164 
wire    layer_4_w22[1:0];
1165 
wire    layer_4_w23[1:0];
1166 
wire    layer_4_w24[1:0];
1167 
wire    layer_4_w25;
1168 
wire    layer_4_w26[1:0];
1169 
wire    layer_4_w27;
1170 
wire    layer_4_w28[1:0];
1171 
wire    layer_4_w29;
1172 
wire    layer_4_w30[1:0];
1173 
wire    layer_4_w31;
1174 
assign  layer_4_w0[0]=layer_3_w0[0];
1175 
assign  layer_4_w0[1]=layer_3_w0[1];
1176 
assign  layer_4_w1=layer_3_w1;
1177 
full_adder      layer_4_full_adder_0(
1178 
layer_3_w2[0],
1179 
layer_3_w2[1],
1180 
layer_3_w2[2],
1181 
layer_4_w2,
1182 
layer_4_w3[0]
1183 
);
1184 
half_adder      layer_4_half_adder_0(
1185 
layer_3_w3[0],
1186 
layer_3_w3[1],
1187 
layer_4_w3[1],
1188 
layer_4_w4[0]
1189 
);
1190 
half_adder      layer_4_half_adder_1(
1191 
layer_3_w4[0],
1192 
layer_3_w4[1],
1193 
layer_4_w4[1],
1194 
layer_4_w5[0]
1195 
);
1196 
half_adder      layer_4_half_adder_2(
1197 
layer_3_w5[0],
1198 
layer_3_w5[1],
1199 
layer_4_w5[1],
1200 
layer_4_w6[0]
1201 
);
1202 
half_adder      layer_4_half_adder_3(
1203 
layer_3_w6[0],
1204 
layer_3_w6[1],
1205 
layer_4_w6[1],
1206 
layer_4_w7[0]
1207 
);
1208 
half_adder      layer_4_half_adder_4(
1209 
layer_3_w7[0],
1210 
layer_3_w7[1],
1211 
layer_4_w7[1],
1212 
layer_4_w8[0]
1213 
);
1214 
half_adder      layer_4_half_adder_5(
1215 
layer_3_w8[0],
1216 
layer_3_w8[1],
1217 
layer_4_w8[1],
1218 
layer_4_w9[0]
1219 
);
1220 
half_adder      layer_4_half_adder_6(
1221 
layer_3_w9[0],
1222 
layer_3_w9[1],
1223 
layer_4_w9[1],
1224 
layer_4_w10[0]
1225 
);
1226 
half_adder      layer_4_half_adder_7(
1227 
layer_3_w10[0],
1228 
layer_3_w10[1],
1229 
layer_4_w10[1],
1230 
layer_4_w11[0]
1231 
);
1232 
half_adder      layer_4_half_adder_8(
1233 
layer_3_w11[0],
1234 
layer_3_w11[1],
1235 
layer_4_w11[1],
1236 
layer_4_w12[0]
1237 
);
1238 
half_adder      layer_4_half_adder_9(
1239 
layer_3_w12[0],
1240 
layer_3_w12[1],
1241 
layer_4_w12[1],
1242 
layer_4_w13[0]
1243 
);
1244 
half_adder      layer_4_half_adder_10(
1245 
layer_3_w13[0],
1246 
layer_3_w13[1],
1247 
layer_4_w13[1],
1248 
layer_4_w14[0]
1249 
);
1250 
half_adder      layer_4_half_adder_11(
1251 
layer_3_w14[0],
1252 
layer_3_w14[1],
1253 
layer_4_w14[1],
1254 
layer_4_w15[0]
1255 
);
1256 
half_adder      layer_4_half_adder_12(
1257 
layer_3_w15[0],
1258 
layer_3_w15[1],
1259 
layer_4_w15[1],
1260 
layer_4_w16[0]
1261 
);
1262 
full_adder      layer_4_full_adder_1(
1263 
layer_3_w16[0],
1264 
layer_3_w16[1],
1265 
layer_3_w16[2],
1266 
layer_4_w16[1],
1267 
layer_4_w17[0]
1268 
);
1269 
half_adder      layer_4_half_adder_13(
1270 
layer_3_w17[0],
1271 
layer_3_w17[1],
1272 
layer_4_w17[1],
1273 
layer_4_w18[0]
1274 
);
1275 
full_adder      layer_4_full_adder_2(
1276 
layer_3_w18[0],
1277 
layer_3_w18[1],
1278 
layer_3_w18[2],
1279 
layer_4_w18[1],
1280 
layer_4_w19[0]
1281 
);
1282 
half_adder      layer_4_half_adder_14(
1283 
layer_3_w19[0],
1284 
layer_3_w19[1],
1285 
layer_4_w19[1],
1286 
layer_4_w20[0]
1287 
);
1288 
full_adder      layer_4_full_adder_3(
1289 
layer_3_w20[0],
1290 
layer_3_w20[1],
1291 
layer_3_w20[2],
1292 
layer_4_w20[1],
1293 
layer_4_w21[0]
1294 
);
1295 
half_adder      layer_4_half_adder_15(
1296 
layer_3_w21[0],
1297 
layer_3_w21[1],
1298 
layer_4_w21[1],
1299 
layer_4_w22[0]
1300 
);
1301 
full_adder      layer_4_full_adder_4(
1302 
layer_3_w22[0],
1303 
layer_3_w22[1],
1304 
layer_3_w22[2],
1305 
layer_4_w22[1],
1306 
layer_4_w23[0]
1307 
);
1308 
half_adder      layer_4_half_adder_16(
1309 
layer_3_w23[0],
1310 
layer_3_w23[1],
1311 
layer_4_w23[1],
1312 
layer_4_w24[0]
1313 
);
1314 
assign  layer_4_w24[1]=layer_3_w24;
1315 
full_adder      layer_4_full_adder_5(
1316 
layer_3_w25[0],
1317 
layer_3_w25[1],
1318 
layer_3_w25[2],
1319 
layer_4_w25,
1320 
layer_4_w26[0]
1321 
);
1322 
assign  layer_4_w26[1]=layer_3_w26;
1323 
full_adder      layer_4_full_adder_6(
1324 
layer_3_w27[0],
1325 
layer_3_w27[1],
1326 
layer_3_w27[2],
1327 
layer_4_w27,
1328 
layer_4_w28[0]
1329 
);
1330 
assign  layer_4_w28[1]=layer_3_w28;
1331 
assign  layer_4_w29=layer_3_w29;
1332 
assign  layer_4_w30[0]=layer_3_w30[0];
1333 
assign  layer_4_w30[1]=layer_3_w30[1];
1334 
assign  layer_4_w31=layer_3_w31;
1335 
 
1336 
//group reduction results into 2 numbers
1337 
wire    [31:0]A,B;
1338 
assign  A[0]=layer_4_w0[0];
1339 
assign  B[0]=layer_4_w0[1];
1340 
assign  A[1]=layer_4_w1;
1341 
assign  B[1]=0;
1342 
assign  A[2]=layer_4_w2;
1343 
assign  B[2]=0;
1344 
assign  A[3]=layer_4_w3[0];
1345 
assign  B[3]=layer_4_w3[1];
1346 
assign  A[4]=layer_4_w4[0];
1347 
assign  B[4]=layer_4_w4[1];
1348 
assign  A[5]=layer_4_w5[0];
1349 
assign  B[5]=layer_4_w5[1];
1350 
assign  A[6]=layer_4_w6[0];
1351 
assign  B[6]=layer_4_w6[1];
1352 
assign  A[7]=layer_4_w7[0];
1353 
assign  B[7]=layer_4_w7[1];
1354 
assign  A[8]=layer_4_w8[0];
1355 
assign  B[8]=layer_4_w8[1];
1356 
assign  A[9]=layer_4_w9[0];
1357 
assign  B[9]=layer_4_w9[1];
1358 
assign  A[10]=layer_4_w10[0];
1359 
assign  B[10]=layer_4_w10[1];
1360 
assign  A[11]=layer_4_w11[0];
1361 
assign  B[11]=layer_4_w11[1];
1362 
assign  A[12]=layer_4_w12[0];
1363 
assign  B[12]=layer_4_w12[1];
1364 
assign  A[13]=layer_4_w13[0];
1365 
assign  B[13]=layer_4_w13[1];
1366 
assign  A[14]=layer_4_w14[0];
1367 
assign  B[14]=layer_4_w14[1];
1368 
assign  A[15]=layer_4_w15[0];
1369 
assign  B[15]=layer_4_w15[1];
1370 
assign  A[16]=layer_4_w16[0];
1371 
assign  B[16]=layer_4_w16[1];
1372 
assign  A[17]=layer_4_w17[0];
1373 
assign  B[17]=layer_4_w17[1];
1374 
assign  A[18]=layer_4_w18[0];
1375 
assign  B[18]=layer_4_w18[1];
1376 
assign  A[19]=layer_4_w19[0];
1377 
assign  B[19]=layer_4_w19[1];
1378 
assign  A[20]=layer_4_w20[0];
1379 
assign  B[20]=layer_4_w20[1];
1380 
assign  A[21]=layer_4_w21[0];
1381 
assign  B[21]=layer_4_w21[1];
1382 
assign  A[22]=layer_4_w22[0];
1383 
assign  B[22]=layer_4_w22[1];
1384 
assign  A[23]=layer_4_w23[0];
1385 
assign  B[23]=layer_4_w23[1];
1386 
assign  A[24]=layer_4_w24[0];
1387 
assign  B[24]=layer_4_w24[1];
1388 
assign  A[25]=layer_4_w25;
1389 
assign  B[25]=0;
1390 
assign  A[26]=layer_4_w26[0];
1391 
assign  B[26]=layer_4_w26[1];
1392 
assign  A[27]=layer_4_w27;
1393 
assign  B[27]=0;
1394 
assign  A[28]=layer_4_w28[0];
1395 
assign  B[28]=layer_4_w28[1];
1396 
assign  A[29]=layer_4_w29;
1397 
assign  B[29]=0;
1398 
assign  A[30]=layer_4_w30[0];
1399 
assign  B[30]=layer_4_w30[1];
1400 
assign  A[31]=layer_4_w31;
1401 
assign  B[31]=0;
1402 
 
1403 
wire    carry;
1404 
adder_32bit     adder_32bit(
1405 
A,
1406 
B,
1407 
1'b0,
1408 
o_product,
1409 
carry
1410 
);
1411 
 
1412 
 
1413 
endmodule

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