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[/] [pif2wb/] [trunk/] [vhdl/] [addr_dec.vhd] - Blame information for rev 12

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Line No. Rev Author Line
1 3 sergio.tot
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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entity AdrDec is
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  generic (
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    constant ADRS_SIZE    :     integer := 32;
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    constant ADRS_BITS    :     integer := 4;
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    constant ADRS_RANGE   :     integer := 8 );
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  port (
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    AdrIn                 : in  std_logic_vector(ADRS_SIZE-1 downto ADRS_SIZE-ADRS_BITS);
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    AdrValid              : out std_logic);
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end AdrDec;
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architecture Behavioral of AdrDec is
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signal Address : std_logic_vector (ADRS_BITS - 1 downto 0);
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begin
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        Address <= conv_std_logic_vector(ADRS_RANGE, ADRS_BITS);
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        process (AdrIn)
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        begin
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                if (AdrIn (ADRS_SIZE - 1 downto ADRS_SIZE - ADRS_BITS) >= Address) then
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                        AdrValid <= '1';
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                else
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                        AdrValid <= '0';
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                end if;
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        end process;
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end Behavioral;

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