URL https://opencores.org/ocsvn/pif2wb/pif2wb/trunk

Subversion Repositories pif2wb

[/] [pif2wb/] [trunk/] [vhdl/] [top_tb.vhd] - Blame information for rev 12

Go to most recent revision | Details | Compare with Previous | View Log


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
 
entity top is
        generic (
                constant DATA_SIZE_PIF : integer := 32;  -- this value specifies the data bus PIF parallelism
                constant DATA_SIZE_WB  : integer := 32;  -- this value specifies the data bus Wishbone parallelism    
                constant ADRS_SIZE     : integer := 32;  -- this value specifies the address bus length
                constant CNTL_PIF      : integer := 8;   -- The PIF CNTL vector size
                constant MSB_PIF       : integer := 31;  -- The PIF most significant bit
                constant LSB_PIF       : integer := 0;   -- The PIF least significant bit 
                constant MSB_WB        : integer := 31;  -- The Wishbone most significant bit
                constant LSB_WB        : integer := 0;   -- The Wishbone least significant bit
                constant ADRS_BITS         : integer := 4;
                constant ADRS_RANGE    : integer := 8
                );
        port (
                SCLK                    : in    STD_LOGIC;
                CLKETH          : in  STD_LOGIC;
                SReset          : in    STD_LOGIC;
 
                PIReqVALID  : in  std_logic;
                PIReqCNTL   : in  std_logic_vector(CNTL_PIF-1 downto 0);
                PIReqADRS   : in  std_logic_vector(ADRS_SIZE-1 downto 0);
                PIReqDATA   : in  std_logic_vector(DATA_SIZE_PIF-1 downto 0);
                PIReqDataBE : in  std_logic_vector(DATA_SIZE_PIF/8-1 downto 0);
                PIRespRDY   : in  std_logic;
 
      probe_mtxd_pad_o   : out std_logic_vector (3 downto 0);
      probe_mtxen_pad_o  : out std_logic;
      mtxerr_pad_o          : out std_logic;
 
      probe_mrxd_pad_i   : in std_logic_vector (3 downto 0);
      probe_mrxdv_pad_i  : in std_logic;
      probe_mrxerr_pad_i : in std_logic;
      probe_mcoll_pad_i  : in std_logic;
      probe_mcrs_pad_i   : in std_logic;
 
      probe_mdc_pad_o    : out std_logic;
      probe_md_pad_i        : in std_logic;
      probe_md_pad_o        : out std_logic;
      probe_md_padoe_o   : out std_logic;
      interrupt             : out std_logic
        );
end top;
 
architecture Structural of top is
 
     -- Pif signals
     signal PIRespValid_t : std_logic ;
     signal PIRespCntl_t : std_logic_vector (7 DOWNTO 0);
     signal PIRespData_t : std_logic_vector (31 DOWNTO 0);
     signal PIRespPriority_t : std_logic_vector (1 DOWNTO 0);
     signal PIRespId_t : std_logic_vector (5 DOWNTO 0);
     signal PIReqRdy_t : std_logic ;
 
     -- Wishbone signals
     signal             data_i : std_logic_vector (31 downto 0);
     signal     data_o : std_logic_vector (31 downto 0);
     signal     addr : std_logic_vector (31 downto 0);
     signal     sel : std_logic_vector (3 downto 0);
     signal     we : std_logic;
     signal     cyc : std_logic;
     signal     stb : std_logic;
     signal     ack : std_logic;
     signal     err : std_logic;
          signal    cti : std_logic_vector (2 downto 0);
          signal    bte : std_logic_vector (1 downto 0);
          signal        m_addr : std_logic_vector (31 downto 0);
     signal     m_sel : std_logic_vector (3 downto 0);
     signal     m_we : std_logic;
     signal     m_data_o : std_logic_vector (31 downto 0);
     signal     m_data_i : std_logic_vector (31 downto 0);
     signal     m_cyc : std_logic;
     signal     m_stb : std_logic;
     signal     m_ack : std_logic;
     signal    m_err : std_logic;
 
   COMPONENT PIF2WB
                generic (
                constant DATA_SIZE_PIF : integer := 32;  -- this value specifies the data bus PIF parallelism
                constant DATA_SIZE_WB  : integer := 32;  -- this value specifies the data bus Wishbone parallelism    
                constant ADRS_SIZE     : integer := 32;  -- this value specifies the address bus length
                constant CNTL_PIF      : integer := 8;   -- The PIF CNTL vector size
                constant MSB_PIF       : integer := 31;  -- The PIF most significant bit
                constant LSB_PIF       : integer := 0;   -- The PIF least significant bit 
                constant MSB_WB        : integer := 31;  -- The Wishbone most significant bit
                constant LSB_WB        : integer := 0;   -- The Wishbone least significant bit
                constant ADRS_BITS         : integer := 4;
                constant ADRS_RANGE    : integer := 8
                );
 
                port (
                CLK     : in std_logic;
                RST     : in std_logic;
 
                PIReqVALID  : in  std_logic;
                PIReqCNTL   : in  std_logic_vector(CNTL_PIF-1 downto 0);
                PIReqADRS   : in  std_logic_vector(ADRS_SIZE-1 downto 0);
                PIReqDATA   : in  std_logic_vector(DATA_SIZE_PIF-1 downto 0);
                PIReqDataBE : in  std_logic_vector(DATA_SIZE_PIF/8-1 downto 0);
                POReqRDY    : out std_logic;
                PORespVALID : out std_logic;
                PORespCNTL  : out std_logic_vector(CNTL_PIF-1 downto 0);
                PORespDATA  : out std_logic_vector(DATA_SIZE_PIF-1 downto 0);
                PIRespRDY   : in  std_logic;
 
                ACK_I : in  std_logic;              -- The acknowledge input
                DAT_I : in  std_logic_vector(DATA_SIZE_WB-1 downto 0);
                ERR_I : in  std_logic;              -- Incates address or data error in transaction
                ADR_O : out std_logic_vector(ADRS_SIZE-1 downto 0);
                DAT_O : out std_logic_vector(DATA_SIZE_WB-1 downto 0);
                CYC_O : out std_logic;              -- The cycle output
                SEL_O : out std_logic_vector(DATA_SIZE_WB/8-1 downto 0);
                STB_O : out std_logic;              -- The strobe output
                WE_O  : out std_logic;              -- The write enable output
                BTE_O : out std_logic_vector(1 downto 0);
                CTI_O : out std_logic_vector(2 downto 0)
                );
        END COMPONENT;
 
        COMPONENT eth_top
    port(
      --WISHBONE common
      wb_clk_i      : in  std_logic;
      wb_rst_i      : in  std_logic;
      wb_dat_i      : in  std_logic_vector(31 downto 0);
      wb_dat_o      : out std_logic_vector(31 downto 0);
      --WISHBONE slave
      wb_adr_i      : in  std_logic_vector(11 downto 2);
      wb_sel_i      : in  std_logic_vector(3 downto 0);
      wb_we_i       : in  std_logic;
      wb_cyc_i      : in  std_logic;
      wb_stb_i      : in  std_logic;
      wb_ack_o      : out std_logic;
      wb_err_o      : out std_logic;
      --WISHBONE master
      m_wb_adr_o    : out std_logic_vector(31 downto 0);
      m_wb_sel_o    : out std_logic_vector(3 downto 0);
      m_wb_we_o     : out std_logic;
      m_wb_dat_o    : out std_logic_vector(31 downto 0);
      m_wb_dat_i    : in  std_logic_vector(31 downto 0);
      m_wb_cyc_o    : out std_logic;
      m_wb_stb_o    : out std_logic;
      m_wb_ack_i    : in  std_logic;
      m_wb_err_i    : in  std_logic;
      --TX
      mtx_clk_pad_i : in  std_logic;
      mtxd_pad_o    : out std_logic_vector(3 downto 0);
      mtxen_pad_o   : out std_logic;
      mtxerr_pad_o  : out std_logic;
      --RX
      mrx_clk_pad_i : in  std_logic;
      mrxd_pad_i    : in  std_logic_vector(3 downto 0);
      mrxdv_pad_i   : in  std_logic;
      mrxerr_pad_i  : in  std_logic;
      mcoll_pad_i   : in  std_logic;
      mcrs_pad_i    : in  std_logic;
      --MIIM
      mdc_pad_o     : out std_logic;
      md_pad_i      : in  std_logic;
      md_pad_o      : out std_logic;
      md_padoe_o    : out std_logic;
      int_o         : out std_logic
      );
  end COMPONENT;
 
begin
 
        pif2wsb:PIF2WB
    port map(
                CLK     => SCLK,
        RST     => SReset,
 
        PIReqVALID  => PIReqVALID,
        PIReqCNTL   => PIReqCNTL,
        PIReqADRS   => PIReqADRS,
        PIReqDATA   => PIReqDATA,
        PIReqDataBE => PIReqDataBE,
        POReqRDY    => PIReqRDY_t,
        PORespVALID => PIRespVALID_t,
        PORespCNTL  => PIRespCNTL_t,
        PORespDATA  => PIRespDATA_t,
        PIRespRDY   => PIRespRDY,
 
        ACK_I => ack,
        DAT_I => data_i,
        ERR_I => err,
        ADR_O => addr,
        DAT_O => data_o,
        CYC_O => cyc,
        SEL_O => sel,
        STB_O => stb,
        WE_O  => we,
        BTE_O => bte,
        CTI_O => cti
                );
 
        eth0 : eth_top
    port map(
      --WISHBONE common
      wb_clk_i      => SCLK,
      wb_rst_i      => SReset,
      wb_dat_i      => data_o,
      wb_dat_o      => data_i,
      --WISHBONE slave
      wb_adr_i      => addr (9 downto 0),
      wb_sel_i      => sel,
      wb_we_i       => we,
      wb_cyc_i      => cyc,
      wb_stb_i      => stb,
      wb_ack_o      => ack,
      wb_err_o      => err,
      --WISHBONE master
      m_wb_adr_o    => m_addr,
      m_wb_sel_o    => m_sel,
      m_wb_we_o     => m_we,
      m_wb_dat_o    => m_data_o,
      m_wb_dat_i    => m_data_i,
      m_wb_cyc_o    => m_cyc,
      m_wb_stb_o    => m_stb,
      m_wb_ack_i    => m_ack,
      m_wb_err_i    => m_err,
      --TX
      mtx_clk_pad_i => CLKETH,
      mtxd_pad_o    => probe_mtxd_pad_o,
      mtxen_pad_o   => probe_mtxen_pad_o,
      mtxerr_pad_o  => mtxerr_pad_o,
      --RX
      mrx_clk_pad_i => CLKETH,
      mrxd_pad_i    => probe_mrxd_pad_i,
      mrxdv_pad_i   => probe_mrxdv_pad_i,
      mrxerr_pad_i  => probe_mrxerr_pad_i,
      mcoll_pad_i   => probe_mcoll_pad_i,
      mcrs_pad_i    => probe_mcrs_pad_i,
      --MIIM
      mdc_pad_o     => probe_mdc_pad_o,
      md_pad_i      => probe_md_pad_i,
      md_pad_o      => probe_md_pad_o,
      md_padoe_o    => probe_md_padoe_o,
      int_o         => interrupt
      );
 
end Structural;
 

Browse

Tools

Subversion Repositories pif2wb

[/] [pif2wb/] [trunk/] [vhdl/] [top_tb.vhd] - Blame information for rev 12

Line No.	Rev	Author	Line
1	5	sergio.tot	`library IEEE;`
2			`use IEEE.STD_LOGIC_1164.ALL;`
3			`use IEEE.STD_LOGIC_ARITH.ALL;`
4			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
5
6
7			`entity top is`
8			`generic (`
9			`constant DATA_SIZE_PIF : integer := 32; -- this value specifies the data bus PIF parallelism`
10			`constant DATA_SIZE_WB : integer := 32; -- this value specifies the data bus Wishbone parallelism`
11			`constant ADRS_SIZE : integer := 32; -- this value specifies the address bus length`
12			`constant CNTL_PIF : integer := 8; -- The PIF CNTL vector size`
13			`constant MSB_PIF : integer := 31; -- The PIF most significant bit`
14			`constant LSB_PIF : integer := 0; -- The PIF least significant bit`
15			`constant MSB_WB : integer := 31; -- The Wishbone most significant bit`
16			`constant LSB_WB : integer := 0; -- The Wishbone least significant bit`
17			`constant ADRS_BITS : integer := 4;`
18			`constant ADRS_RANGE : integer := 8`
19			`);`
20			`port (`
21			`SCLK : in STD_LOGIC;`
22			`CLKETH : in STD_LOGIC;`
23			`SReset : in STD_LOGIC;`
24
25			`PIReqVALID : in std_logic;`
26			`PIReqCNTL : in std_logic_vector(CNTL_PIF-1 downto 0);`
27			`PIReqADRS : in std_logic_vector(ADRS_SIZE-1 downto 0);`
28			`PIReqDATA : in std_logic_vector(DATA_SIZE_PIF-1 downto 0);`
29			`PIReqDataBE : in std_logic_vector(DATA_SIZE_PIF/8-1 downto 0);`
30			`PIRespRDY : in std_logic;`
31
32			`probe_mtxd_pad_o : out std_logic_vector (3 downto 0);`
33			`probe_mtxen_pad_o : out std_logic;`
34			`mtxerr_pad_o : out std_logic;`
35
36			`probe_mrxd_pad_i : in std_logic_vector (3 downto 0);`
37			`probe_mrxdv_pad_i : in std_logic;`
38			`probe_mrxerr_pad_i : in std_logic;`
39			`probe_mcoll_pad_i : in std_logic;`
40			`probe_mcrs_pad_i : in std_logic;`
41
42			`probe_mdc_pad_o : out std_logic;`
43			`probe_md_pad_i : in std_logic;`
44			`probe_md_pad_o : out std_logic;`
45			`probe_md_padoe_o : out std_logic;`
46			`interrupt : out std_logic`
47			`);`
48			`end top;`
49
50			`architecture Structural of top is`
51
52			`-- Pif signals`
53			`signal PIRespValid_t : std_logic ;`
54			`signal PIRespCntl_t : std_logic_vector (7 DOWNTO 0);`
55			`signal PIRespData_t : std_logic_vector (31 DOWNTO 0);`
56			`signal PIRespPriority_t : std_logic_vector (1 DOWNTO 0);`
57			`signal PIRespId_t : std_logic_vector (5 DOWNTO 0);`
58			`signal PIReqRdy_t : std_logic ;`
59
60			`-- Wishbone signals`
61			`signal data_i : std_logic_vector (31 downto 0);`
62			`signal data_o : std_logic_vector (31 downto 0);`
63			`signal addr : std_logic_vector (31 downto 0);`
64			`signal sel : std_logic_vector (3 downto 0);`
65			`signal we : std_logic;`
66			`signal cyc : std_logic;`
67			`signal stb : std_logic;`
68			`signal ack : std_logic;`
69			`signal err : std_logic;`
70			`signal cti : std_logic_vector (2 downto 0);`
71			`signal bte : std_logic_vector (1 downto 0);`
72			`signal m_addr : std_logic_vector (31 downto 0);`
73			`signal m_sel : std_logic_vector (3 downto 0);`
74			`signal m_we : std_logic;`
75			`signal m_data_o : std_logic_vector (31 downto 0);`
76			`signal m_data_i : std_logic_vector (31 downto 0);`
77			`signal m_cyc : std_logic;`
78			`signal m_stb : std_logic;`
79			`signal m_ack : std_logic;`
80			`signal m_err : std_logic;`
81
82			`COMPONENT PIF2WB`
83			`generic (`
84			`constant DATA_SIZE_PIF : integer := 32; -- this value specifies the data bus PIF parallelism`
85			`constant DATA_SIZE_WB : integer := 32; -- this value specifies the data bus Wishbone parallelism`
86			`constant ADRS_SIZE : integer := 32; -- this value specifies the address bus length`
87			`constant CNTL_PIF : integer := 8; -- The PIF CNTL vector size`
88			`constant MSB_PIF : integer := 31; -- The PIF most significant bit`
89			`constant LSB_PIF : integer := 0; -- The PIF least significant bit`
90			`constant MSB_WB : integer := 31; -- The Wishbone most significant bit`
91			`constant LSB_WB : integer := 0; -- The Wishbone least significant bit`
92			`constant ADRS_BITS : integer := 4;`
93			`constant ADRS_RANGE : integer := 8`
94			`);`
95
96			`port (`
97			`CLK : in std_logic;`
98			`RST : in std_logic;`
99
100			`PIReqVALID : in std_logic;`
101			`PIReqCNTL : in std_logic_vector(CNTL_PIF-1 downto 0);`
102			`PIReqADRS : in std_logic_vector(ADRS_SIZE-1 downto 0);`
103			`PIReqDATA : in std_logic_vector(DATA_SIZE_PIF-1 downto 0);`
104			`PIReqDataBE : in std_logic_vector(DATA_SIZE_PIF/8-1 downto 0);`
105			`POReqRDY : out std_logic;`
106			`PORespVALID : out std_logic;`
107			`PORespCNTL : out std_logic_vector(CNTL_PIF-1 downto 0);`
108			`PORespDATA : out std_logic_vector(DATA_SIZE_PIF-1 downto 0);`
109			`PIRespRDY : in std_logic;`
110
111			`ACK_I : in std_logic; -- The acknowledge input`
112			`DAT_I : in std_logic_vector(DATA_SIZE_WB-1 downto 0);`
113			`ERR_I : in std_logic; -- Incates address or data error in transaction`
114			`ADR_O : out std_logic_vector(ADRS_SIZE-1 downto 0);`
115			`DAT_O : out std_logic_vector(DATA_SIZE_WB-1 downto 0);`
116			`CYC_O : out std_logic; -- The cycle output`
117			`SEL_O : out std_logic_vector(DATA_SIZE_WB/8-1 downto 0);`
118			`STB_O : out std_logic; -- The strobe output`
119			`WE_O : out std_logic; -- The write enable output`
120			`BTE_O : out std_logic_vector(1 downto 0);`
121			`CTI_O : out std_logic_vector(2 downto 0)`
122			`);`
123			`END COMPONENT;`
124
125			`COMPONENT eth_top`
126			`port(`
127			`--WISHBONE common`
128			`wb_clk_i : in std_logic;`
129			`wb_rst_i : in std_logic;`
130			`wb_dat_i : in std_logic_vector(31 downto 0);`
131			`wb_dat_o : out std_logic_vector(31 downto 0);`
132			`--WISHBONE slave`
133			`wb_adr_i : in std_logic_vector(11 downto 2);`
134			`wb_sel_i : in std_logic_vector(3 downto 0);`
135			`wb_we_i : in std_logic;`
136			`wb_cyc_i : in std_logic;`
137			`wb_stb_i : in std_logic;`
138			`wb_ack_o : out std_logic;`
139			`wb_err_o : out std_logic;`
140			`--WISHBONE master`
141			`m_wb_adr_o : out std_logic_vector(31 downto 0);`
142			`m_wb_sel_o : out std_logic_vector(3 downto 0);`
143			`m_wb_we_o : out std_logic;`
144			`m_wb_dat_o : out std_logic_vector(31 downto 0);`
145			`m_wb_dat_i : in std_logic_vector(31 downto 0);`
146			`m_wb_cyc_o : out std_logic;`
147			`m_wb_stb_o : out std_logic;`
148			`m_wb_ack_i : in std_logic;`
149			`m_wb_err_i : in std_logic;`
150			`--TX`
151			`mtx_clk_pad_i : in std_logic;`
152			`mtxd_pad_o : out std_logic_vector(3 downto 0);`
153			`mtxen_pad_o : out std_logic;`
154			`mtxerr_pad_o : out std_logic;`
155			`--RX`
156			`mrx_clk_pad_i : in std_logic;`
157			`mrxd_pad_i : in std_logic_vector(3 downto 0);`
158			`mrxdv_pad_i : in std_logic;`
159			`mrxerr_pad_i : in std_logic;`
160			`mcoll_pad_i : in std_logic;`
161			`mcrs_pad_i : in std_logic;`
162			`--MIIM`
163			`mdc_pad_o : out std_logic;`
164			`md_pad_i : in std_logic;`
165			`md_pad_o : out std_logic;`
166			`md_padoe_o : out std_logic;`
167			`int_o : out std_logic`
168			`);`
169			`end COMPONENT;`
170
171			`begin`
172
173			`pif2wsb:PIF2WB`
174			`port map(`
175			`CLK => SCLK,`
176			`RST => SReset,`
177
178			`PIReqVALID => PIReqVALID,`
179			`PIReqCNTL => PIReqCNTL,`
180			`PIReqADRS => PIReqADRS,`
181			`PIReqDATA => PIReqDATA,`
182			`PIReqDataBE => PIReqDataBE,`
183			`POReqRDY => PIReqRDY_t,`
184			`PORespVALID => PIRespVALID_t,`
185			`PORespCNTL => PIRespCNTL_t,`
186			`PORespDATA => PIRespDATA_t,`
187			`PIRespRDY => PIRespRDY,`
188
189			`ACK_I => ack,`
190			`DAT_I => data_i,`
191			`ERR_I => err,`
192			`ADR_O => addr,`
193			`DAT_O => data_o,`
194			`CYC_O => cyc,`
195			`SEL_O => sel,`
196			`STB_O => stb,`
197			`WE_O => we,`
198			`BTE_O => bte,`
199			`CTI_O => cti`
200			`);`
201
202			`eth0 : eth_top`
203			`port map(`
204			`--WISHBONE common`
205			`wb_clk_i => SCLK,`
206			`wb_rst_i => SReset,`
207			`wb_dat_i => data_o,`
208			`wb_dat_o => data_i,`
209			`--WISHBONE slave`
210			`wb_adr_i => addr (9 downto 0),`
211			`wb_sel_i => sel,`
212			`wb_we_i => we,`
213			`wb_cyc_i => cyc,`
214			`wb_stb_i => stb,`
215			`wb_ack_o => ack,`
216			`wb_err_o => err,`
217			`--WISHBONE master`
218			`m_wb_adr_o => m_addr,`
219			`m_wb_sel_o => m_sel,`
220			`m_wb_we_o => m_we,`
221			`m_wb_dat_o => m_data_o,`
222			`m_wb_dat_i => m_data_i,`
223			`m_wb_cyc_o => m_cyc,`
224			`m_wb_stb_o => m_stb,`
225			`m_wb_ack_i => m_ack,`
226			`m_wb_err_i => m_err,`
227			`--TX`
228			`mtx_clk_pad_i => CLKETH,`
229			`mtxd_pad_o => probe_mtxd_pad_o,`
230			`mtxen_pad_o => probe_mtxen_pad_o,`
231			`mtxerr_pad_o => mtxerr_pad_o,`
232			`--RX`
233			`mrx_clk_pad_i => CLKETH,`
234			`mrxd_pad_i => probe_mrxd_pad_i,`
235			`mrxdv_pad_i => probe_mrxdv_pad_i,`
236			`mrxerr_pad_i => probe_mrxerr_pad_i,`
237			`mcoll_pad_i => probe_mcoll_pad_i,`
238			`mcrs_pad_i => probe_mcrs_pad_i,`
239			`--MIIM`
240			`mdc_pad_o => probe_mdc_pad_o,`
241			`md_pad_i => probe_md_pad_i,`
242			`md_pad_o => probe_md_pad_o,`
243			`md_padoe_o => probe_md_padoe_o,`
244			`int_o => interrupt`
245			`);`
246
247			`end Structural;`
248