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/////////////////////////////////////////////////////////////////////
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//// ////
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//// FFT/IFFT 128 points transform ////
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//// ////
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//// Authors: Anatoliy Sergienko, Volodya Lepeha ////
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//// Company: Unicore Systems http://unicore.co.ua ////
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//// ////
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//// Downloaded from: http://www.opencores.org ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2006-2010 Unicore Systems LTD ////
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//// www.unicore.co.ua ////
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//// o.uzenkov@unicore.co.ua ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// THIS SOFTWARE IS PROVIDED "AS IS" ////
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//// AND ANY EXPRESSED OR IMPLIED WARRANTIES, ////
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//// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ////
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//// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ////
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//// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ////
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//// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ////
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//// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ////
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//// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ////
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//// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ////
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//// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ////
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//// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ////
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//// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ////
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//// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ////
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//// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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// DESCRIPTION : Top level of the high speed FFT core
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// FUNCTION: Structural model of the high speed 128-complex point FFT
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// core intended for synthesizing
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// for any type FPGAs and ASIC.
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// FILES: FFT128.v - root unit, this file,
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// FFT128_CONFIG.inc - core configuration file
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// BUFRAM128C.v - 1-st,2-nd,3-d data buffer, contains:
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// RAM2x128C.v - dual ported synchronous RAM, contains:
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// RAM128.v -single ported synchronous RAM
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// FFT16.v- 1-st,2-nd stages implementing 16-point FFTs, contains
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// MPU707.v, MPU707_2.v - multiplier to the factor 0.707.
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// ROTATOR256.v - unit for rotating complex vectors, contains
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// WROM256.v - ROM of twiddle factors.
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// CNORM.v - normalization stages
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// UNFFT256_TB.v - testbench file, includes:
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// Wave_ROM256.v - ROM with input data and result reference data
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// SineROM256_gen.pl - PERL script to generate the Wave_ROM256.v file
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//
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// PROPERTIES: 1. Fully pipelined, 1 complex data in, 1 complex result out each clock cycle
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// 2. Input data, output data, coefficient widths are adjustable in range 8..16
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// 3. Normalization stages trigger the data overflow and shift data right
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// to prevent the overflow
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// 4. Core can contain 2 or 3 data buffers. In the configuration of 2 buffers
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// the results are in the shuffled order but provided with the proper address.
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// 5. The core operation can be slowed down by the control of the ED input
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// 6. The reset RST is synchronous one
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//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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`timescale 1 ns / 1 ps
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`include "FFT128_CONFIG.inc"
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module FFT128 ( CLK ,RST ,ED ,START ,SHIFT ,DR ,DI ,RDY ,OVF1 ,OVF2 ,ADDR ,DOR ,DOI );
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`FFT128paramnb //nb is the data bit width
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output RDY ; // in the next cycle after RDY=1 the 0-th result is present
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wire RDY ;
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output OVF1 ; // 1 signals that an overflow occured in the 1-st stage
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wire OVF1 ;
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output OVF2 ; // 1 signals that an overflow occured in the 2-nd stage
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wire OVF2 ;
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output [6:0] ADDR ; //result data address/number
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wire [6:0] ADDR ;
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output [nb+3:0] DOR ;//Real part of the output data,
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wire [nb+3:0] DOR ; // the bit width is nb+4, can be decreased when instantiating the core
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output [nb+3:0] DOI ;//Imaginary part of the output data
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wire [nb+3:0] DOI ;
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input CLK ; //Clock signal is less than 300 MHz for the Xilinx Virtex5 FPGA
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wire CLK ;
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input RST ; //Reset signal, is the synchronous one with respect to CLK
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wire RST ;
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input ED ; //=1 enables the operation (eneabling CLK)
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wire ED ;
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input START ; // its falling edge starts the transform or the serie of transforms
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wire START ; // and resets the overflow detectors
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input [3:0] SHIFT ; // bits 1,0 -shift left code in the 1-st stage
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wire [3:0] SHIFT ; // bits 3,2 -shift left code in the 2-nd stage
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input [nb-1:0] DR ; // Real part of the input data, 0-th data goes just after
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wire [nb-1:0] DR ; // the START signal or after 255-th data of the previous transform
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input [nb-1:0] DI ; //Imaginary part of the input data
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wire [nb-1:0] DI ;
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wire [nb-1:0] dr1,di1;
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wire [nb+1:0] dr3,di3,dr4,di4, dr5,di5 ;
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wire [nb+2:0] dr2,di2;
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wire [nb+5:0] dr6,di6;
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wire [nb+3:0] dr7,di7,dr8,di8;
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wire rdy1,rdy2,rdy3,rdy4,rdy5,rdy6,rdy7,rdy8;
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reg [7:0] addri ;
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// input buffer =8-bit inversion ordering
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BUFRAM128C_1 #(nb) U_BUF1(.CLK(CLK), .RST(RST), .ED(ED), .START(START),
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.DR(DR), .DI(DI), .RDY(rdy1), .DOR(dr1), .DOI(di1));
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//1-st stage of FFT
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FFT8 #(nb) U_FFT1(.CLK(CLK), .RST(RST), .ED(ED),
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.START(rdy1),.DIR(dr1),.DII(di1),
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.RDY(rdy2), .DOR(dr2),. DOI(di2));
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wire [1:0] shiftl= SHIFT[1:0];
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CNORM_1 #(nb) U_NORM1( .CLK(CLK), .ED(ED), //1-st normalization unit
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.START(rdy2), // overflow detector reset
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.DR(dr2), .DI(di2),
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.SHIFT(shiftl), //shift left bit number
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.OVF(OVF1),
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.RDY(rdy3),
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.DOR(dr3),.DOI(di3));
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// rotator to the angles proportional to PI/64
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ROTATOR128 #(nb+2) U_MPU (.CLK(CLK),.RST(RST),.ED(ED),
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.START(rdy3),. DR(dr3),.DI(di3),
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.RDY(rdy4), .DOR(dr4), .DOI(di4));
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BUFRAM128C_2 #(nb+2) U_BUF2(.CLK(CLK),.RST(RST),.ED(ED), // intermediate buffer =8-bit inversion ordering
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.START(rdy4),. DR(dr4),.DI(di4),
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.RDY(rdy5), .DOR(dr5), .DOI(di5));
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//2-nd stage of FFT
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FFT16 #(nb+2) U_FFT2(.CLK(CLK), .RST(RST), .ED(ED),
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.START(rdy5),. DIR(dr5),.DII(di5),
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.RDY(rdy6), .DOR(dr6), .DOI(di6));
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wire [1:0] shifth= SHIFT[3:2];
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//2-nd normalization unit
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CNORM_2 #(nb+2) U_NORM2 ( .CLK(CLK), .ED(ED),
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.START(rdy6), // overflow detector reset
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.DR(dr6), .DI(di6),
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.SHIFT(shifth), //shift left bit number
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.OVF(OVF2),
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.RDY(rdy7),
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.DOR(dr7), .DOI(di7));
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BUFRAM128C #(nb+4) Ubuf3(.CLK(CLK),.RST(RST),.ED(ED), // intermediate buffer =8-bit inversion ordering
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.START(rdy7),. DR(dr7),.DI(di7),
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.RDY(rdy8), .DOR(dr8), .DOI(di8));
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`ifdef FFT128parambuffers3 // 3-data buffer configuratiion
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always @(posedge CLK) begin //POINTER to the result samples
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if (RST)
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addri<=7'b000_0000;
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else if (rdy8==1 )
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addri<=7'b000_0000;
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else if (ED)
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addri<=addri+1;
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end
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assign ADDR= addri ;
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assign DOR=dr8;
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assign DOI=di8;
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assign RDY=rdy8;
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`else
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always @(posedge CLK) begin //POINTER to the result samples
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if (RST)
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addri<=7'b000_0000;
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else if (rdy7)
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addri<=7'b000_0000;
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else if (ED)
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addri<=addri+1;
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end
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assign #1 ADDR= {addri[2:0] , addri[6:3]} ;
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assign #2 DOR= dr7;
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assign #2 DOI= di7;
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assign RDY= rdy7;
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`endif
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endmodule
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