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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  8-point FFT, First stage of FFT 64 processor               ////
////                                                             ////
////  Authors: Anatoliy Sergienko, Volodya Lepeha                ////
////  Company: Unicore Systems http://unicore.co.ua              ////
////                                                             ////
////  Downloaded from: http://www.opencores.org                  ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2006-2010 Unicore Systems LTD                 ////
//// www.unicore.co.ua                                           ////
//// o.uzenkov@unicore.co.ua                                     ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
//// THIS SOFTWARE IS PROVIDED "AS IS"                           ////
//// AND ANY EXPRESSED OR IMPLIED WARRANTIES,                    ////
//// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED                  ////
//// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT              ////
//// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.        ////
//// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS                ////
//// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,            ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL            ////
//// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT         ////
//// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,               ////
//// DATA, OR PROFITS; OR BUSINESS INTERRUPTION)                 ////
//// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,              ////
//// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT              ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING                 ////
//// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,                 ////
//// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.          ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
// Design_Version       : 1.0
// File name            : FFT8.v
// File Revision        : 
// Last modification    : Sun Sep 30 20:11:56 2007
/////////////////////////////////////////////////////////////////////
// FUNCTION: 8-point FFT
// FILES: FFT8.v - 1-st stage, contains
//        MPU707.v - multiplier to the factor 0.707.
// PROPERTIES:1) Fully pipelined
//                2) Each clock cycle complex datum is entered
//               and complex result is outputted
//                3) Has 8-clock cycle period starting with the START 
//               impulse and continuing forever
//                4) rounding   is not used
//                5)Algorithm is from the book "H.J.Nussbaumer FFT and 
//              convolution algorithms".
//                6)IFFT is performed by substituting the output result 
//              order to the reversed one
//                  (by exchanging - to + and + to -)
/////////////////////////////////////////////////////////////////////
//Algorithm:
//  procedure FFT8(
//               D: in MEMOC8;  -- input array
//               DO:out MEMOC8)  -- output ARRAY
//              is   
//              variable t1,t2,t3,t4,t5,t6,t7,t8,m0,m1,m2,m3,m4,m5,m6,m7: complex;
//              variable s1,s2,s3,s4: complex;
//      begin                                              
//              t1:=D(0) + D(4);
//              m3:=D(0) - D(4);
//              t2:=D(6) + D(2);
//          m6:=CBASE_j*(D(6)-D(2));
//              t3:=D(1) + D(5);
//              t4:=D(1) - D(5);
//              t5:=D(3) + D(7);
//              t6:=D(3) - D(7);
//              t8:=t5 + t3;
//              m5:=CBASE_j*(t5-t3);
//              t7:=t1 + t2;
//              m2:=t1 - t2;
//              m0:=t7 + t8;
//              m1:=t7 - t8;      
//              m4:=SQRT(0.5)*(t4 - t6);
//              m7:=-CBASE_j*SQRT(0.5)*(t4 + t6);          
//              s1:=m3 + m4;
//              s2:=m3 - m4;
//              s3:=m6 + m7;
//              s4:=m6 - m7;
//              DO(0):=m0;
//              DO(4):=m1;
//              DO(1):=s1 + s3;
//              DO(7):=s1 - s3;
//              DO(2):=m2 + m5;
//              DO(6):=m2 - m5;
//              DO(5):=s2 + s4;
//              DO(3):=s2 - s4;
//      end procedure;  
/////////////////////////////////////////////////////////////////////
`timescale 1ps / 1ps
`include "FFT64_CONFIG.inc"
 
module FFT8 ( DOR ,DII ,RST ,ED ,CLK ,DOI ,START ,DIR ,RDY );
        `USFFT64paramnb
 
        input ED ;
        wire ED ;
        input RST ;
        wire RST ;
        input CLK ;
        wire CLK ;
        input [nb-1:0] DII ;
        wire [nb-1:0] DII ;
        input START ;
        wire START ;
        input [nb-1:0] DIR ;
        wire [nb-1:0] DIR ;
 
        output [nb+2:0] DOI ;
        wire [nb+2:0] DOI ;
        output [nb+2:0] DOR ;
        wire [nb+2:0] DOR ;
        output RDY ;
        reg RDY ;
 
        reg [2:0] ct; //main phase counter
        reg [3:0] ctd; //delay counter
 
        always @(   posedge CLK) begin  //Control counter
                        //
                        if (RST)        begin
                                        ct<=0;
                                        ctd<=15;
                                RDY<=0;  end
                        else if (START)   begin
                                        ct<=0;
                                        ctd<=0;
                                RDY<=0;   end
                        else if (ED) begin
                                        RDY<=0;
                                        ct<=ct+1;
                                        if (ctd !=4'b1111)
                                                ctd<=ctd+1;
                                        if (ctd==12 )
                                                RDY<=1;
                                end
 
                end
 
        reg signed      [nb-1: 0] dr,d1r,d2r,d3r,d4r,di,d1i,d2i,d3i,d4i;
        always @(posedge CLK)     // input register file
                begin
                        if (ED)         begin
                                        dr<=DIR;
                                        d1r<=dr;
                                        d2r<=d1r;
                                        d3r<=d2r;
                                        d4r<=d3r;
                                        di<=DII;
                                        d1i<=di;
                                        d2i<=d1i;
                                        d3i<=d2i;
                                        d4i<=d3i;
                                end
                end
 
        reg signed      [nb:0]   s1r,s2r,s1d1r,s1d2r,s1d3r,s2d1r,s2d2r,s2d3r;
        reg signed      [nb:0]   s1i,s2i,s1d1i,s1d2i,s1d3i,s2d1i,s2d2i,s2d3i;
        always @(posedge CLK)   begin              // S1,S2 =t1-t6,m3 and delayed
                        if (ED && ((ct==5) || (ct==6) || (ct==7) || (ct==0))) begin
                                        s1r<=d4r + dr ;
                                        s1i<=d4i + di ;
                                        s2r<=d4r - dr ;
                                        s2i<= d4i - di;
                                end
                        if      (ED)   begin
                                        s1d1r<=s1r;
                                        s1d2r<=s1d1r;
                                        s1d1i<=s1i;
                                        s1d2i<=s1d1i;
                                        if (ct==0 || ct==1)       begin    //## note for vhdl
                                                        s1d3r<=s1d2r;
                                                        s1d3i<=s1d2i;
                                                end
                                        if (ct==6 || ct==7 || ct==0) begin
                                                        s2d1r<=s2r;
                                                        s2d2r<=s2d1r;
                                                        s2d1i<=s2i;
                                                        s2d2i<=s2d1i;
                                                end
                                        if (ct==0) begin
                                                        s2d3r<=s2d2r;
                                                        s2d3i<=s2d2i;
                                                end
                                end
                end
 
 
        reg signed [nb+1:0]      s3r,s4r,s3d1r,s3d2r,s3d3r;
        reg signed [nb+1:0]      s3i,s4i,s3d1i,s3d2i,s3d3i;
        always @(posedge CLK)   begin             //ALU S3:     
                        if (ED)
                                case (ct)
                                        0: begin s3r<=  s1d2r+s1r;                  //t7
                                                s3i<= s1d2i+ s1i ;end
                                        1: begin s3r<=  s1d3r - s1d1r;           //m2
                                                s3i<= s1d3i - s1d1i; end
                                        2: begin s3r<= s1d3r +s1r;               //t8
                                                s3i<= s1d3i+ s1i ; end
                                        3: begin s3r<=  s1d3r - s1r;             //
                                                s3i<= s1d3i - s1i ; end
                                endcase
 
                        if      (ED) begin
                                        if (ct==1 || ct==2 || ct==3) begin
                                                        s3d1r<=s3r;                                             //t8
                                                        s3d1i<=s3i;
                                                end
                                        if ( ct==2 || ct==3) begin
                                                        s3d2r<=s3d1r;                                   //m2
                                                        s3d3r<=s3d2r;                              //t7
                                                        s3d2i<=s3d1i;
                                                        s3d3i<=s3d2i;
                                                end
                                end
                end
 
        always @ (posedge CLK)  begin             // S4 
                        if (ED) begin
                                        if (ct==1) begin
                                                        s4r<= s2d2r + s2r;
                                                s4i<= s2d2i + s2i; end
                                        else if (ct==2) begin
                                                        s4r<=s2d2r - s2r;
                                                        s4i<= s2d2i - s2i;
                                                end
                                end
                end
 
        assign  em = ((ct==2 || ct==3 || ct==4)&& ED);
 
        wire signed [nb+1:0] m4m7r,m4m7i;
        MPU707 #(nb) UMR( .CLK(CLK),.EI(em),.DI(s4r),.DO(m4m7r));        //  UMR
        MPU707 #(nb) UMI( .CLK(CLK),.EI(em),.DI(s4i),   .DO(m4m7i));     //  UMR
 
        reg signed [nb+1:0]      sjr,sji, m6r,m6i;
        always @ (posedge CLK)  begin              //multiply by J 
                        if (ED) begin
                                        case  (ct)
                                                3: begin sjr<= s2d1i;                   //m6
                                                        sji<=0 - s2d1r; end
                                                4: begin sjr<= m4m7i;   //m7
                                                        sji<=0 - m4m7r;end
                                                6: begin sjr<= s3i;             //m5
                                                        sji<=0 - s3r;      end
                                        endcase
                                        if (ct==4) begin
                                                        m6r<=sjr;                                //m6
                                                        m6i<=sji;
                                                end
                                end
                end
 
        reg     signed [nb+2:0]  s5r,s5d1r,s5d2r,q1r;
        reg     signed [nb+2:0]  s5i,s5d1i,s5d2i,q1i;
        always @ (posedge CLK)               //         S5:
                if (ED)
                        case  (ct)
                                5: begin q1r<=s2d3r +m4m7r ;       //    S1
                                                q1i<=s2d3i +m4m7i ;
                                                s5r<=m6r + sjr;
                                        s5i<=m6i + sji; end
                                6: begin        s5r<=m6r - sjr;
                                                s5i<=m6i - sji;
                                                s5d1r<=s5r;
                                        s5d1i<=s5i; end
                                7: begin         s5r<=s2d3r - m4m7r;
                                                s5i<=s2d3i - m4m7i;
                                                s5d1r<=s5r;
                                                s5d1i<=s5i;
                                                s5d2r<=s5d1r;
                                                s5d2i<=s5d1i;
                                        end
                        endcase
 
        reg     signed [nb+3:0]  s6r,s6i ;
        `ifdef paramifft
        always @ (posedge CLK)  begin            //  S6-- result adder
                        if (ED)
                                case  (ct)
                                        5: begin s6r<=s3d3r +s3d1r ;      // --  D0
                                                s6i<=s3d3i +s3d1i ;end     //--  D0
                                        6: begin
                                                                s6r<=q1r - s5r ;
                                                        s6i<=q1i - s5i ;         end
                                        7:  begin
                                                                s6r<=s3d2r - sjr ;
                                                        s6i<=s3d2i - sji ;        end
                                        0:  begin
                                                                s6r<=s5r + s5d1r ;
                                                        s6i<= s5i +s5d1i ;      end
                                        1:begin s6r<=s3d3r - s3d1r ;        //--         D4
                                                s6i<=s3d3i - s3d1i ; end
                                        2: begin
                                                                s6r<= s5r - s5d1r ;            //        D5
                                                        s6i<= s5i - s5d1i ;        end
                                        3: begin                                                            //   D6
                                                                s6r<=s3d3r + sjr ;
                                                                s6i<=s3d3i + sji ;
                                                        end
                                        4:   begin                                                                         //    D0
                                                                s6r<= q1r + s5d2r ;
                                                                s6i<= q1i + s5d2i ;
                                                        end
                                endcase
                end
 
   `else
                        always @ (posedge CLK)  begin            //  S6-- result adder
                        if (ED)
                                case  (ct)
                                        5: begin s6r<=s3d3r +s3d1r ;      // --  D0
                                                s6i<=s3d3i +s3d1i ;end     //--  D0
                                        6:  begin
                                                                s6r<=q1r + s5r ;                     //--        D1
                                                        s6i<=q1i + s5i ; end
                                                7:   begin
                                                                s6r<=s3d2r +sjr ;                //--    D2
                                                        s6i<=s3d2i +sji ;          end
                                        0:   begin
                                                                s6r<=s5r - s5d1r ;                     // --     D3
                                                        s6i<= s5i - s5d1i ;end
 
                                        1:begin s6r<=s3d3r - s3d1r ;        //--         D4
                                                s6i<=s3d3i - s3d1i ; end
                                        2:   begin
                                                                s6r<=s5r + s5d1r ;                    //--       D5
                                                        s6i<=s5i + s5d1i ; end
 
                                        3:  begin
                                                                s6r<= s3d3r - sjr ;             //       D6
                                                        s6i<=s3d3i - sji ;      end
 
                                        4:   begin
                                                                s6r<= q1r - s5d2r ;              //      D0
                                                        s6i<=  q1i - s5d2i ;    end
 
                                endcase
                end
        `endif
 
        assign #1       DOR=s6r[nb+2:0];
        assign #1       DOI= s6i[nb+2:0];
 
endmodule

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[/] [pipelined_fft_64/] [trunk/] [RTL/] [fft8.v] - Blame information for rev 12

Line No.	Rev	Author	Line
1	8	unicore	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// 8-point FFT, First stage of FFT 64 processor ////`
4			`//// ////`
5			`//// Authors: Anatoliy Sergienko, Volodya Lepeha ////`
6			`//// Company: Unicore Systems http://unicore.co.ua ////`
7			`//// ////`
8			`//// Downloaded from: http://www.opencores.org ////`
9			`//// ////`
10			`/////////////////////////////////////////////////////////////////////`
11			`//// ////`
12			`//// Copyright (C) 2006-2010 Unicore Systems LTD ////`
13			`//// www.unicore.co.ua ////`
14			`//// o.uzenkov@unicore.co.ua ////`
15			`//// ////`
16			`//// This source file may be used and distributed without ////`
17			`//// restriction provided that this copyright statement is not ////`
18			`//// removed from the file and that any derivative work contains ////`
19			`//// the original copyright notice and the associated disclaimer.////`
20			`//// ////`
21			`//// THIS SOFTWARE IS PROVIDED "AS IS" ////`
22			`//// AND ANY EXPRESSED OR IMPLIED WARRANTIES, ////`
23			`//// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ////`
24			`//// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ////`
25			`//// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ////`
26			`//// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ////`
27			`//// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
28			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ////`
29			`//// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ////`
30			`//// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ////`
31			`//// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ////`
32			`//// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ////`
33			`//// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
34			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ////`
35			`//// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ////`
36			`//// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ////`
37			`//// ////`
38			`/////////////////////////////////////////////////////////////////////`
39			`// Design_Version : 1.0`
40			`// File name : FFT8.v`
41			`// File Revision :`
42			`// Last modification : Sun Sep 30 20:11:56 2007`
43			`/////////////////////////////////////////////////////////////////////`
44			`// FUNCTION: 8-point FFT`
45			`// FILES: FFT8.v - 1-st stage, contains`
46			`// MPU707.v - multiplier to the factor 0.707.`
47			`// PROPERTIES:1) Fully pipelined`
48			`// 2) Each clock cycle complex datum is entered`
49			`// and complex result is outputted`
50			`// 3) Has 8-clock cycle period starting with the START`
51			`// impulse and continuing forever`
52			`// 4) rounding is not used`
53			`// 5)Algorithm is from the book "H.J.Nussbaumer FFT and`
54			`// convolution algorithms".`
55			`// 6)IFFT is performed by substituting the output result`
56			`// order to the reversed one`
57			`// (by exchanging - to + and + to -)`
58			`/////////////////////////////////////////////////////////////////////`
59			`//Algorithm:`
60			`// procedure FFT8(`
61			`// D: in MEMOC8; -- input array`
62			`// DO:out MEMOC8) -- output ARRAY`
63			`// is`
64			`// variable t1,t2,t3,t4,t5,t6,t7,t8,m0,m1,m2,m3,m4,m5,m6,m7: complex;`
65			`// variable s1,s2,s3,s4: complex;`
66			`// begin`
67			`// t1:=D(0) + D(4);`
68			`// m3:=D(0) - D(4);`
69			`// t2:=D(6) + D(2);`
70			`// m6:=CBASE_j*(D(6)-D(2));`
71			`// t3:=D(1) + D(5);`
72			`// t4:=D(1) - D(5);`
73			`// t5:=D(3) + D(7);`
74			`// t6:=D(3) - D(7);`
75			`// t8:=t5 + t3;`
76			`// m5:=CBASE_j*(t5-t3);`
77			`// t7:=t1 + t2;`
78			`// m2:=t1 - t2;`
79			`// m0:=t7 + t8;`
80			`// m1:=t7 - t8;`
81			`// m4:=SQRT(0.5)*(t4 - t6);`
82			`// m7:=-CBASE_jSQRT(0.5)(t4 + t6);`
83			`// s1:=m3 + m4;`
84			`// s2:=m3 - m4;`
85			`// s3:=m6 + m7;`
86			`// s4:=m6 - m7;`
87			`// DO(0):=m0;`
88			`// DO(4):=m1;`
89			`// DO(1):=s1 + s3;`
90			`// DO(7):=s1 - s3;`
91			`// DO(2):=m2 + m5;`
92			`// DO(6):=m2 - m5;`
93			`// DO(5):=s2 + s4;`
94			`// DO(3):=s2 - s4;`
95			`// end procedure;`
96			`/////////////////////////////////////////////////////////////////////`
97			`timescale 1ps / 1ps
98			`include "FFT64_CONFIG.inc"
99
100			`module FFT8 ( DOR ,DII ,RST ,ED ,CLK ,DOI ,START ,DIR ,RDY );`
101			`USFFT64paramnb
102
103			`input ED ;`
104			`wire ED ;`
105			`input RST ;`
106			`wire RST ;`
107			`input CLK ;`
108			`wire CLK ;`
109			`input [nb-1:0] DII ;`
110			`wire [nb-1:0] DII ;`
111			`input START ;`
112			`wire START ;`
113			`input [nb-1:0] DIR ;`
114			`wire [nb-1:0] DIR ;`
115
116			`output [nb+2:0] DOI ;`
117			`wire [nb+2:0] DOI ;`
118			`output [nb+2:0] DOR ;`
119			`wire [nb+2:0] DOR ;`
120			`output RDY ;`
121			`reg RDY ;`
122
123			`reg [2:0] ct; //main phase counter`
124			`reg [3:0] ctd; //delay counter`
125
126			`always @( posedge CLK) begin //Control counter`
127			`//`
128			`if (RST) begin`
129			`ct<=0;`
130			`ctd<=15;`
131			`RDY<=0; end`
132			`else if (START) begin`
133			`ct<=0;`
134			`ctd<=0;`
135			`RDY<=0; end`
136			`else if (ED) begin`
137			`RDY<=0;`
138			`ct<=ct+1;`
139			`if (ctd !=4'b1111)`
140			`ctd<=ctd+1;`
141			`if (ctd==12 )`
142			`RDY<=1;`
143			`end`
144
145			`end`
146
147			`reg signed [nb-1: 0] dr,d1r,d2r,d3r,d4r,di,d1i,d2i,d3i,d4i;`
148			`always @(posedge CLK) // input register file`
149			`begin`
150			`if (ED) begin`
151			`dr<=DIR;`
152			`d1r<=dr;`
153			`d2r<=d1r;`
154			`d3r<=d2r;`
155			`d4r<=d3r;`
156			`di<=DII;`
157			`d1i<=di;`
158			`d2i<=d1i;`
159			`d3i<=d2i;`
160			`d4i<=d3i;`
161			`end`
162			`end`
163
164			`reg signed [nb:0] s1r,s2r,s1d1r,s1d2r,s1d3r,s2d1r,s2d2r,s2d3r;`
165			`reg signed [nb:0] s1i,s2i,s1d1i,s1d2i,s1d3i,s2d1i,s2d2i,s2d3i;`
166			`always @(posedge CLK) begin // S1,S2 =t1-t6,m3 and delayed`
167			`if (ED && ((ct==5) \|\| (ct==6) \|\| (ct==7) \|\| (ct==0))) begin`
168			`s1r<=d4r + dr ;`
169			`s1i<=d4i + di ;`
170			`s2r<=d4r - dr ;`
171			`s2i<= d4i - di;`
172			`end`
173			`if (ED) begin`
174			`s1d1r<=s1r;`
175			`s1d2r<=s1d1r;`
176			`s1d1i<=s1i;`
177			`s1d2i<=s1d1i;`
178			`if (ct==0 \|\| ct==1) begin //## note for vhdl`
179			`s1d3r<=s1d2r;`
180			`s1d3i<=s1d2i;`
181			`end`
182			`if (ct==6 \|\| ct==7 \|\| ct==0) begin`
183			`s2d1r<=s2r;`
184			`s2d2r<=s2d1r;`
185			`s2d1i<=s2i;`
186			`s2d2i<=s2d1i;`
187			`end`
188			`if (ct==0) begin`
189			`s2d3r<=s2d2r;`
190			`s2d3i<=s2d2i;`
191			`end`
192			`end`
193			`end`
194
195
196			`reg signed [nb+1:0] s3r,s4r,s3d1r,s3d2r,s3d3r;`
197			`reg signed [nb+1:0] s3i,s4i,s3d1i,s3d2i,s3d3i;`
198			`always @(posedge CLK) begin //ALU S3:`
199			`if (ED)`
200			`case (ct)`
201			`0: begin s3r<= s1d2r+s1r; //t7`
202			`s3i<= s1d2i+ s1i ;end`
203			`1: begin s3r<= s1d3r - s1d1r; //m2`
204			`s3i<= s1d3i - s1d1i; end`
205			`2: begin s3r<= s1d3r +s1r; //t8`
206			`s3i<= s1d3i+ s1i ; end`
207			`3: begin s3r<= s1d3r - s1r; //`
208			`s3i<= s1d3i - s1i ; end`
209			`endcase`
210
211			`if (ED) begin`
212			`if (ct==1 \|\| ct==2 \|\| ct==3) begin`
213			`s3d1r<=s3r; //t8`
214			`s3d1i<=s3i;`
215			`end`
216			`if ( ct==2 \|\| ct==3) begin`
217			`s3d2r<=s3d1r; //m2`
218			`s3d3r<=s3d2r; //t7`
219			`s3d2i<=s3d1i;`
220			`s3d3i<=s3d2i;`
221			`end`
222			`end`
223			`end`
224
225			`always @ (posedge CLK) begin // S4`
226			`if (ED) begin`
227			`if (ct==1) begin`
228			`s4r<= s2d2r + s2r;`
229			`s4i<= s2d2i + s2i; end`
230			`else if (ct==2) begin`
231			`s4r<=s2d2r - s2r;`
232			`s4i<= s2d2i - s2i;`
233			`end`
234			`end`
235			`end`
236
237			`assign em = ((ct==2 \|\| ct==3 \|\| ct==4)&& ED);`
238
239			`wire signed [nb+1:0] m4m7r,m4m7i;`
240			`MPU707 #(nb) UMR( .CLK(CLK),.EI(em),.DI(s4r),.DO(m4m7r)); // UMR`
241			`MPU707 #(nb) UMI( .CLK(CLK),.EI(em),.DI(s4i), .DO(m4m7i)); // UMR`
242
243			`reg signed [nb+1:0] sjr,sji, m6r,m6i;`
244			`always @ (posedge CLK) begin //multiply by J`
245			`if (ED) begin`
246			`case (ct)`
247			`3: begin sjr<= s2d1i; //m6`
248			`sji<=0 - s2d1r; end`
249			`4: begin sjr<= m4m7i; //m7`
250			`sji<=0 - m4m7r;end`
251			`6: begin sjr<= s3i; //m5`
252			`sji<=0 - s3r; end`
253			`endcase`
254			`if (ct==4) begin`
255			`m6r<=sjr; //m6`
256			`m6i<=sji;`
257			`end`
258			`end`
259			`end`
260
261			`reg signed [nb+2:0] s5r,s5d1r,s5d2r,q1r;`
262			`reg signed [nb+2:0] s5i,s5d1i,s5d2i,q1i;`
263			`always @ (posedge CLK) // S5:`
264			`if (ED)`
265			`case (ct)`
266			`5: begin q1r<=s2d3r +m4m7r ; // S1`
267			`q1i<=s2d3i +m4m7i ;`
268			`s5r<=m6r + sjr;`
269			`s5i<=m6i + sji; end`
270			`6: begin s5r<=m6r - sjr;`
271			`s5i<=m6i - sji;`
272			`s5d1r<=s5r;`
273			`s5d1i<=s5i; end`
274			`7: begin s5r<=s2d3r - m4m7r;`
275			`s5i<=s2d3i - m4m7i;`
276			`s5d1r<=s5r;`
277			`s5d1i<=s5i;`
278			`s5d2r<=s5d1r;`
279			`s5d2i<=s5d1i;`
280			`end`
281			`endcase`
282
283			`reg signed [nb+3:0] s6r,s6i ;`
284			`ifdef paramifft
285			`always @ (posedge CLK) begin // S6-- result adder`
286			`if (ED)`
287			`case (ct)`
288			`5: begin s6r<=s3d3r +s3d1r ; // -- D0`
289			`s6i<=s3d3i +s3d1i ;end //-- D0`
290			`6: begin`
291			`s6r<=q1r - s5r ;`
292			`s6i<=q1i - s5i ; end`
293			`7: begin`
294			`s6r<=s3d2r - sjr ;`
295			`s6i<=s3d2i - sji ; end`
296			`0: begin`
297			`s6r<=s5r + s5d1r ;`
298			`s6i<= s5i +s5d1i ; end`
299			`1:begin s6r<=s3d3r - s3d1r ; //-- D4`
300			`s6i<=s3d3i - s3d1i ; end`
301			`2: begin`
302			`s6r<= s5r - s5d1r ; // D5`
303			`s6i<= s5i - s5d1i ; end`
304			`3: begin // D6`
305			`s6r<=s3d3r + sjr ;`
306			`s6i<=s3d3i + sji ;`
307			`end`
308			`4: begin // D0`
309			`s6r<= q1r + s5d2r ;`
310			`s6i<= q1i + s5d2i ;`
311			`end`
312			`endcase`
313			`end`
314
315			`else
316			`always @ (posedge CLK) begin // S6-- result adder`
317			`if (ED)`
318			`case (ct)`
319			`5: begin s6r<=s3d3r +s3d1r ; // -- D0`
320			`s6i<=s3d3i +s3d1i ;end //-- D0`
321			`6: begin`
322			`s6r<=q1r + s5r ; //-- D1`
323			`s6i<=q1i + s5i ; end`
324			`7: begin`
325			`s6r<=s3d2r +sjr ; //-- D2`
326			`s6i<=s3d2i +sji ; end`
327			`0: begin`
328			`s6r<=s5r - s5d1r ; // -- D3`
329			`s6i<= s5i - s5d1i ;end`
330
331			`1:begin s6r<=s3d3r - s3d1r ; //-- D4`
332			`s6i<=s3d3i - s3d1i ; end`
333			`2: begin`
334			`s6r<=s5r + s5d1r ; //-- D5`
335			`s6i<=s5i + s5d1i ; end`
336
337			`3: begin`
338			`s6r<= s3d3r - sjr ; // D6`
339			`s6i<=s3d3i - sji ; end`
340
341			`4: begin`
342			`s6r<= q1r - s5d2r ; // D0`
343			`s6i<= q1i - s5d2i ; end`
344
345			`endcase`
346			`end`
347			`endif
348
349			`assign #1 DOR=s6r[nb+2:0];`
350			`assign #1 DOI= s6i[nb+2:0];`
351
352			`endmodule`