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/////////////////////////////////////////////////////////////////////
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//// ////
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//// 1-port synchronous RAM ////
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//// ////
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//// Authors: Anatoliy Sergienko, Volodya Lepeha ////
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//// Company: Unicore Systems http://unicore.co.ua ////
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//// ////
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//// Downloaded from: http://www.opencores.org ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2006-2010 Unicore Systems LTD ////
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//// www.unicore.co.ua ////
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//// o.uzenkov@unicore.co.ua ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// THIS SOFTWARE IS PROVIDED "AS IS" ////
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//// AND ANY EXPRESSED OR IMPLIED WARRANTIES, ////
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//// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ////
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//// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ////
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//// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ////
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//// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ////
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//// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ////
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//// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ////
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//// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ////
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//// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ////
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//// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ////
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//// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ////
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//// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ////
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//// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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// Design_Version : 1.0
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// File name : RAM64.v
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// File Revision :
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// Last modification : Sun Sep 30 20:11:56 2007
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/////////////////////////////////////////////////////////////////////
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// FUNCTION: 1-port synchronous RAM
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// FILES: RAM64.v -single ported synchronous RAM
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// PROPERTIES: 1) Has the volume of 64 data
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// 2) RAM is synchronous one, the read datum is outputted
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// in 2 cycles after the address setting
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// 3) Can be substituted to any 2-port synchronous RAM
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/////////////////////////////////////////////////////////////////////
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`timescale 1 ns / 1 ps
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`include "FFT64_CONFIG.inc"
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module RAM64 ( CLK, ED,WE ,ADDR ,DI ,DO );
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`USFFT64paramnb
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output [nb-1:0] DO ;
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reg [nb-1:0] DO ;
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input CLK ;
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wire CLK ;
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input ED;
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input WE ;
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wire WE ;
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input [5:0] ADDR ;
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wire [5:0] ADDR ;
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input [nb-1:0] DI ;
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wire [nb-1:0] DI ;
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reg [nb-1:0] mem [63:0];
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reg [5:0] addrrd;
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always @(posedge CLK) begin
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if (ED) begin
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if (WE) mem[ADDR] <= DI;
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addrrd <= ADDR; //storing the address
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DO <= mem[addrrd]; // registering the read datum
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end
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end
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endmodule
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