OpenCores
URL https://opencores.org/ocsvn/pit/pit/trunk

Subversion Repositories pit

[/] [pit/] [trunk/] [bench/] [sys_verilog/] [tst_bench_top.sv] - Blame information for rev 24

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 23 rehayes
////////////////////////////////////////////////////////////////////////////////
2
//
3
//  WISHBONE revB.2 compliant Programable Interval Timer - Test Bench
4
//
5
//  Author: Bob Hayes
6
//          rehayes@opencores.org
7
//
8
//  Downloaded from: http://www.opencores.org/projects/pit.....
9
//
10
////////////////////////////////////////////////////////////////////////////////
11
// Copyright (c) 2011, Robert Hayes
12
//
13
// All rights reserved.
14
//
15
// Redistribution and use in source and binary forms, with or without
16
// modification, are permitted provided that the following conditions are met:
17
//     * Redistributions of source code must retain the above copyright
18
//       notice, this list of conditions and the following disclaimer.
19
//     * Redistributions in binary form must reproduce the above copyright
20
//       notice, this list of conditions and the following disclaimer in the
21
//       documentation and/or other materials provided with the distribution.
22
//     * Neither the name of the  nor the
23
//       names of its contributors may be used to endorse or promote products
24
//       derived from this software without specific prior written permission.
25
//
26
// THIS SOFTWARE IS PROVIDED BY Robert Hayes ''AS IS'' AND ANY
27
// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
28
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
29
// DISCLAIMED. IN NO EVENT SHALL Robert Hayes BE LIABLE FOR ANY
30
// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
31
// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
32
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
33
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
35
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36
////////////////////////////////////////////////////////////////////////////////
37
// 45678901234567890123456789012345678901234567890123456789012345678901234567890
38
 
39
`include "timescale.v"
40
 
41
module tst_bench_top();
42
 
43
  parameter STOP_ON_ERROR = 1'b0;
44
  parameter MAX_VECTOR = 1_000;
45
  //
46
  // wires && regs
47
  //
48
  logic        mstr_test_clk;
49
  logic [19:0] vector;
50
  logic [ 7:0] test_num;
51
  logic        rstn;
52
  logic        sync_reset;
53
 
54
  logic [31:0] adr;
55
  logic [15:0] dat_i, dat_o, dat0_i, dat1_i, dat2_i, dat3_i;
56
  logic we;
57
  logic stb;
58
  logic cyc;
59
  logic ack, ack_1, ack_2, ack_3, ack_4;
60
  logic inta_1, inta_2, inta_3, inta_4;
61
  logic count_en_1;
62
  logic count_flag_1;
63
 
64
  logic [15:0] q, qq;
65
  logic [15:0] error_count;
66
 
67
  logic scl, scl0_o, scl0_oen, scl1_o, scl1_oen;
68
  logic sda, sda0_o, sda0_oen, sda1_o, sda1_oen;
69
 
70 24 rehayes
  // Name the Address Locations of the PIT Wishbone control registers
71 23 rehayes
  parameter PIT_CNTRL = 5'b0_0000;
72
  parameter PIT_MOD   = 5'b0_0001;
73
  parameter PIT_COUNT = 5'b0_0010;
74
 
75
  parameter RD      = 1'b1;
76
  parameter WR      = 1'b0;
77
  parameter SADR    = 7'b0010_000;
78
 
79
  parameter CTR_EN  = 8'b1000_0000;  // core enable bit
80
  parameter CTR_IEN = 8'b0100_0000;  // core interrupt enable bit
81
 
82 24 rehayes
  // Name the control/status bits of the PIT registers
83 23 rehayes
  parameter PIT_CNTRL_SLAVE  = 16'h8000;  // PIT Slave mode
84
  parameter PIT_CNTRL_FLAG   = 16'h0004;  // PIT Rollover Flag
85
  parameter PIT_CNTRL_IRQEN  = 16'h0002;  // PIT Interupt Enable
86
  parameter PIT_CNTRL_ENA    = 16'h0001;  // PIT Enable
87
 
88 24 rehayes
  parameter SLAVE_0_CNTRL = 5'b0_1000 + PIT_CNTRL;
89
  parameter SLAVE_0_MOD   = 5'b0_1000 + PIT_MOD;
90
  parameter SLAVE_0_COUNT = 5'b0_1000 + PIT_COUNT;
91 23 rehayes
 
92 24 rehayes
  parameter SLAVE_1_CNTRL = 5'b1_0000 + PIT_CNTRL;
93
  parameter SLAVE_1_MOD   = 5'b1_0000 + PIT_MOD;
94
  parameter SLAVE_1_COUNT = 5'b1_0000 + PIT_COUNT;
95 23 rehayes
 
96
  parameter SLAVE_2_CNTRL_0 = 5'b1_1000;
97
  parameter SLAVE_2_CNTRL_1 = 5'b1_1001;
98
  parameter SLAVE_2_MOD_0   = 5'b1_1010;
99
  parameter SLAVE_2_MOD_1   = 5'b1_1011;
100
  parameter SLAVE_2_COUNT_0 = 5'b1_1100;
101
  parameter SLAVE_2_COUNT_1 = 5'b1_1101;
102
 
103
  // initial values and testbench setup
104
  initial
105
    begin
106 24 rehayes
      mstr_test_clk <= 0;
107
      vector        <= 0;
108
      test_num      <= 0;
109
      error_count   <= 0;
110 23 rehayes
 
111
      `ifdef WAVES
112
           $shm_open("waves");
113
           $shm_probe("AS",tst_bench_top,"AS");
114
           $display("\nINFO: Signal dump enabled ...\n\n");
115
      `endif
116
 
117
      `ifdef WAVES_V
118
           $dumpfile ("pit_wave_dump.lxt");
119
           $dumpvars (0, tst_bench_top);
120
           $dumpon;
121
           $display("\nINFO: VCD Signal dump enabled ...\n\n");
122
      `endif
123
 
124
      `ifdef DEBUSSY
125
           $fsdbDumpfile("pit_wave_dump.fsdb");
126
           $fsdbDumpvars(0);
127
           $display("\nINFO: Debussy Signal dump enabled ...\n\n");
128
      `endif
129
 
130
    end
131
 
132
  // generate clock
133
  always #20 mstr_test_clk = ~mstr_test_clk;
134
 
135
  // Keep a count of how many clocks we've simulated
136
  always @(posedge mstr_test_clk)
137
    begin
138
      vector <= vector + 1;
139
      if (vector > MAX_VECTOR)
140
        begin
141
          error_count <= error_count + 1;
142
          $display("\n ------ !!!!! Simulation Timeout at vector=%d\n -------", vector);
143
          wrap_up;
144
        end
145
    end
146
 
147
  // Add up errors tha come from WISHBONE read compares
148 24 rehayes
  always @master.cmp_error_detect
149 23 rehayes
    begin
150
      error_count <= error_count + 1;
151
    end
152
 
153 24 rehayes
  // Define a seperate interface for each PIT instance since each PIT
154
  // intstance has small differences
155
  wishbone_if #(.D_WIDTH (16),
156
                .A_WIDTH (3))
157
               wb_1(
158
              .wb_clk   (mstr_test_clk),
159
              .wb_rst   (1'b0),
160
              .arst     (rstn));
161
 
162
  wishbone_if  wb_2(
163
              .wb_clk   (mstr_test_clk),
164
              .wb_rst   (sync_reset),
165
              .arst     (1'b0));
166
 
167
  wishbone_if  wb_3(
168
              .wb_clk   (mstr_test_clk),
169
              .wb_rst   (sync_reset),
170
              .arst     (1'b1));
171
 
172
  wishbone_if #(.D_WIDTH (8))
173
               wb_4(
174
              .wb_clk   (mstr_test_clk),
175
              .wb_rst   (sync_reset),
176
              .arst     (1'b1));
177
 
178 23 rehayes
  // hookup wishbone master model
179
  wb_master_model #(.dwidth(16), .awidth(32))
180 24 rehayes
          master (
181
          .wb_1(wb_1),
182
          .wb_2(wb_2),
183
          .wb_3(wb_3),
184
          .wb_4(wb_4),
185 23 rehayes
          .clk(mstr_test_clk),
186
          .rst(rstn),
187
          .adr(adr),
188
          .din(dat_i),
189
          .dout(dat_o),
190
          .cyc(cyc),
191
          .stb(stb),
192
          .we(we),
193
          .sel(),
194
          .ack(ack),
195
          .err(1'b0),
196
          .rty(1'b0)
197
  );
198
 
199
 
200
  // Address decoding for different PIT module instances
201
  wire stb0 = stb && ~adr[4] && ~adr[3];
202
  wire stb1 = stb && ~adr[4] &&  adr[3];
203
  wire stb2 = stb &&  adr[4] && ~adr[3];
204
  wire stb3 = stb &&  adr[4] &&  adr[3];
205
 
206
  // Create the Read Data Bus
207
  assign dat_i = ({16{stb0}} & dat0_i) |
208
                 ({16{stb1}} & dat1_i) |
209
                 ({16{stb2}} & dat2_i) |
210
                 ({16{stb3}} & {8'b0, dat3_i[7:0]});
211
 
212
  assign ack = ack_1 || ack_2 || ack_3 || ack_4;
213
 
214 24 rehayes
 
215
  // hookup wishbone_PIT_slave core - Parameters take all default values
216 23 rehayes
  //  Async Reset, 16 bit Bus, 16 bit Granularity,Wait States
217 24 rehayes
  pit_top pit_1(
218 23 rehayes
          // wishbone interface
219 24 rehayes
          .wb        (wb_1),
220
          .wb_dat_o  (dat0_i),
221
          .wb_stb    (stb0),
222
          .wb_ack    (ack_1),
223 23 rehayes
 
224 24 rehayes
          .pit_irq_o (inta_1),
225
          .pit_o     (pit_1_out),
226 23 rehayes
          .ext_sync_i(1'b0),
227
          .cnt_sync_o(count_en_1),
228
          .cnt_flag_o(count_flag_1)
229
  );
230
 
231
  // hookup wishbone_PIT_slave core - Parameters take all default values
232
  //  Sync Reset, 16 bit Bus, 16 bit Granularity
233
  pit_top #(.ARST_LVL(1'b1))
234
          pit_2(
235
          // wishbone interface
236 24 rehayes
          .wb      (wb_2),
237 23 rehayes
          .wb_dat_o(dat1_i),
238 24 rehayes
          .wb_stb  (stb1),
239
          .wb_ack  (ack_2),
240
 
241 23 rehayes
          .pit_irq_o(inta_2),
242
          .pit_o(pit_2_out),
243
          .ext_sync_i(count_en_1),
244
          .cnt_sync_o(count_en_2),
245
          .cnt_flag_o(count_flag_2)
246
  );
247
 
248
  // hookup wishbone_PIT_slave core
249
  //  16 bit Bus, 16 bit Granularity
250
  pit_top #(.NO_PRESCALE(1'b1))
251
          pit_3(
252
          // wishbone interface
253 24 rehayes
          .wb      (wb_3),
254 23 rehayes
          .wb_dat_o(dat2_i),
255 24 rehayes
          .wb_stb  (stb2),
256
          .wb_ack  (ack_3),
257
 
258 23 rehayes
          .pit_irq_o(inta_3),
259
          .pit_o(pit_3_out),
260
          .ext_sync_i(count_en_1),
261
          .cnt_sync_o(count_en_3),
262
          .cnt_flag_o(count_flag_3)
263
  );
264
 
265
  // hookup wishbone_PIT_slave core
266
  //  8 bit Bus, 8 bit Granularity
267 24 rehayes
  pit_top #(.D_WIDTH(8))
268 23 rehayes
          pit_4(
269
          // wishbone interface
270 24 rehayes
          .wb      (wb_4),
271 23 rehayes
          .wb_dat_o(dat3_i[7:0]),
272 24 rehayes
          .wb_stb  (stb3),
273
          .wb_ack  (ack_4),
274
 
275 23 rehayes
          .pit_irq_o(inta_4),
276
          .pit_o(pit_4_out),
277
          .ext_sync_i(count_en_1),
278
          .cnt_sync_o(count_en_4),
279
          .cnt_flag_o(count_flag_4)
280
  );
281
 
282 24 rehayes
// Main Test Program -----------------------------------------------------------
283 23 rehayes
initial
284
  begin
285
      $display("\nstatus: %t Testbench started", $time);
286
 
287
      // reset system
288
      rstn = 1'b1; // negate reset
289
      repeat(1) @(posedge mstr_test_clk);
290
      sync_reset = 1'b1;  // Make the sync reset 1 clock cycle long
291
      #2;          // move the async reset away from the clock edge
292
      rstn = 1'b0; // assert async reset
293
      #5;          // Keep the async reset pulse with less than a clock cycle
294
      rstn = 1'b1; // negate async reset
295
      repeat(1) @(posedge mstr_test_clk);
296
      sync_reset = 1'b0;
297
 
298
      $display("\nstatus: %t done reset", $time);
299
      test_num = test_num + 1;
300
 
301
      repeat(2) @(posedge mstr_test_clk);
302
 
303
      //
304
      // program core
305
      //
306
 
307
      reg_test_16;
308
 
309
      reg_test_8;
310
 
311 24 rehayes
      master.wb_write(1, SLAVE_0_CNTRL,   PIT_CNTRL_SLAVE); // Enable Slave Mode
312
      master.wb_write(1, SLAVE_1_CNTRL,   PIT_CNTRL_SLAVE); // Enable Slave Mode
313
      master.wb_write(1, SLAVE_2_CNTRL_1, 16'h0080); // Enable Slave Mode
314
      master.wb_write(1, SLAVE_0_MOD,     16'h000a); // load Modulo
315
      master.wb_write(1, SLAVE_1_MOD,     16'h0010); // load Modulo
316
      master.wb_write(1, SLAVE_2_MOD_0,   16'h0010); // load Modulo
317 23 rehayes
 
318
      // Set Master Mode PS=0, Modulo=16
319
      test_num = test_num + 1;
320
      $display("TEST #%d Starts at vector=%d, ms_test", test_num, vector);
321
 
322 24 rehayes
      master.wb_write(1, PIT_MOD,   16'h0010); // load prescaler hi-byte
323
      master.wb_write(1, PIT_CNTRL, PIT_CNTRL_ENA); // Enable to start counting
324 23 rehayes
      $display("status: %t programmed registers", $time);
325
 
326
      wait_flag_set;  // Wait for Counter to tomeout
327 24 rehayes
      master.wb_write(1, PIT_CNTRL, PIT_CNTRL_FLAG | PIT_CNTRL_ENA); //
328 23 rehayes
 
329
      wait_flag_set;  // Wait for Counter to tomeout
330 24 rehayes
      master.wb_write(1, PIT_CNTRL, PIT_CNTRL_FLAG | PIT_CNTRL_ENA); //
331 23 rehayes
 
332
      repeat(10) @(posedge mstr_test_clk);
333 24 rehayes
      master.wb_write(1, PIT_CNTRL, 16'b0); //
334 23 rehayes
 
335
      repeat(10) @(posedge mstr_test_clk);
336
 
337
      mstr_psx_modx(2,4);
338
 
339
      mstr_psx_modx(4,0);
340
 
341
      repeat(100) @(posedge mstr_test_clk);
342
 
343
      wrap_up;
344
 
345 24 rehayes
  end  // Main Test Flow  ------------------------------------------------------
346 23 rehayes
 
347
// Poll for flag set
348
task wait_flag_set;
349 24 rehayes
  master.wb_read(1, PIT_CNTRL, q);
350 23 rehayes
  while(~|(q & PIT_CNTRL_FLAG))
351 24 rehayes
    master.wb_read(1, PIT_CNTRL, q); // poll it until it is set
352 23 rehayes
  $display("PIT Flag set detected at vector =%d", vector);
353
endtask
354
 
355
// check register bits - reset, read/write
356
task reg_test_16;
357
  test_num = test_num + 1;
358
  $display("TEST #%d Starts at vector=%d, reg_test_16", test_num, vector);
359 24 rehayes
  master.wb_cmp(0, PIT_CNTRL, 16'h4000);   // verify reset
360
  master.wb_cmp(0, PIT_MOD,   16'h0000);   // verify reset
361
  master.wb_cmp(0, PIT_COUNT, 16'h0001);   // verify reset
362 23 rehayes
 
363 24 rehayes
  master.wb_write(1, PIT_CNTRL, 16'hfffe); // load prescaler lo-byte
364
  master.wb_cmp(  0, PIT_CNTRL, 16'hCf02); // verify write data
365
  master.wb_write(1, PIT_CNTRL, 16'h0000); // load prescaler lo-byte
366
  master.wb_cmp(  0, PIT_CNTRL, 16'h4000); // verify write data
367 23 rehayes
 
368 24 rehayes
  master.wb_write(1, PIT_MOD, 16'h5555); // load prescaler lo-byte
369
  master.wb_cmp(  0, PIT_MOD, 16'h5555); // verify write data
370
  master.wb_write(1, PIT_MOD, 16'haaaa); // load prescaler lo-byte
371
  master.wb_cmp(  0, PIT_MOD, 16'haaaa); // verify write data
372 23 rehayes
 
373 24 rehayes
  master.wb_write(0, PIT_COUNT, 16'hfffe);
374
  master.wb_cmp(  0, PIT_COUNT, 16'h0001); // verify register not writable
375 23 rehayes
endtask
376
 
377 24 rehayes
// Check the registers when the PIT is configured for 8-bit mode
378 23 rehayes
task reg_test_8;
379
  test_num = test_num + 1;
380
  $display("TEST #%d Starts at vector=%d, reg_test_8", test_num, vector);
381 24 rehayes
  master.wb_cmp(0, SLAVE_2_CNTRL_0, 16'h0000);   // verify reset
382
  master.wb_cmp(0, SLAVE_2_CNTRL_1, 16'h0040);   // verify reset
383
  master.wb_cmp(0, SLAVE_2_MOD_0,   16'h0000);   // verify reset
384
  master.wb_cmp(0, SLAVE_2_MOD_1,   16'h0000);   // verify reset
385
  master.wb_cmp(0, SLAVE_2_COUNT_0, 16'h0001);   // verify reset
386
  master.wb_cmp(0, SLAVE_2_COUNT_1, 16'h0000);   // verify reset
387 23 rehayes
 
388 24 rehayes
  master.wb_write(1, SLAVE_2_CNTRL_0, 16'hfffe); // load prescaler lo-byte
389
  master.wb_cmp(  0, SLAVE_2_CNTRL_0, 16'h0002); // verify write data
390
  master.wb_write(1, SLAVE_2_CNTRL_0, 16'h0000); // load prescaler lo-byte
391
  master.wb_cmp(  0, SLAVE_2_CNTRL_0, 16'h0000); // verify write data
392
  master.wb_cmp(  0, SLAVE_2_CNTRL_1, 16'h0040); // verify write data
393 23 rehayes
 
394 24 rehayes
  master.wb_write(1, SLAVE_2_MOD_0, 16'hff55); // load prescaler lo-byte
395
  master.wb_cmp(  0, SLAVE_2_MOD_0, 16'h0055); // verify write data
396
  master.wb_write(1, SLAVE_2_MOD_0, 16'hffaa); // load prescaler lo-byte
397
  master.wb_cmp(  0, SLAVE_2_MOD_0, 16'h00aa); // verify write data
398
  master.wb_write(1, SLAVE_2_MOD_1, 16'hff66); // load prescaler lo-byte
399
  master.wb_cmp(  0, SLAVE_2_MOD_1, 16'h0066); // verify write data
400
  master.wb_write(1, SLAVE_2_MOD_1, 16'hff99); // load prescaler lo-byte
401
  master.wb_cmp(  0, SLAVE_2_MOD_1, 16'h0099); // verify write data
402
  master.wb_write(1, SLAVE_2_MOD_1, 16'hff00); // load prescaler lo-byte
403 23 rehayes
 
404 24 rehayes
  master.wb_write(0, SLAVE_2_COUNT_0, 16'hfffe);
405
  master.wb_cmp(  0, SLAVE_2_COUNT_0, 16'h0001); // verify register not writable
406
  master.wb_write(0, SLAVE_2_COUNT_1, 16'hfffe);
407
  master.wb_cmp(  0, SLAVE_2_COUNT_1, 16'h0000); // verify register not writable
408 23 rehayes
endtask
409
 
410
task mstr_psx_modx(
411
  logic [ 3:0] ps_val,
412
  logic [15:0] mod_val);
413
  logic [15:0] cntrl_val;
414
  test_num = test_num + 1;
415
  $display("TEST #%d Starts at vector=%d, mstr_psx_modx Pre=%h, Mod=%h",
416
          test_num, vector, ps_val, mod_val);
417
  // program internal registers
418
 
419
  cntrl_val = {1'b0, 3'b0, ps_val, 8'b0} | PIT_CNTRL_IRQEN;
420 24 rehayes
  master.wb_write(1, PIT_MOD,   mod_val); // load modulo
421
  master.wb_write(1, PIT_CNTRL, ( cntrl_val | PIT_CNTRL_ENA)); // Enable to start counting
422 23 rehayes
 
423
  wait_flag_set;  // Wait for Counter to timeout
424 24 rehayes
  master.wb_write(1, PIT_CNTRL, cntrl_val | PIT_CNTRL_FLAG | PIT_CNTRL_ENA); //
425 23 rehayes
 
426
  wait_flag_set;  // Wait for Counter to timeout
427 24 rehayes
  master.wb_write(1, PIT_CNTRL, cntrl_val | PIT_CNTRL_FLAG | PIT_CNTRL_ENA); //
428 23 rehayes
 
429
  repeat(10) @(posedge mstr_test_clk);
430
 
431 24 rehayes
  master.wb_write(1, PIT_CNTRL, 16'b0); //
432 23 rehayes
endtask
433
 
434 24 rehayes
// End the simulation and print out the final results
435 23 rehayes
task wrap_up;
436
  test_num = test_num + 1;
437
  repeat(10) @(posedge mstr_test_clk);
438
  $display("\nSimulation Finished!! - vector =%d", vector);
439
  if (error_count == 0)
440
  $display("Simulation Passed");
441
  else
442
  $display("Simulation Failed  --- Errors =%d", error_count);
443
 
444
  $finish;
445
endtask
446
 
447
 
448
endmodule  // tst_bench_top
449
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.