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1 23 rehayes
////////////////////////////////////////////////////////////////////////////////
2
//
3
//  WISHBONE revB.2 compliant Programable Interval Timer - Test Bench
4
//
5
//  Author: Bob Hayes
6
//          rehayes@opencores.org
7
//
8
//  Downloaded from: http://www.opencores.org/projects/pit.....
9
//
10
////////////////////////////////////////////////////////////////////////////////
11
// Copyright (c) 2011, Robert Hayes
12
//
13
// All rights reserved.
14
//
15
// Redistribution and use in source and binary forms, with or without
16
// modification, are permitted provided that the following conditions are met:
17
//     * Redistributions of source code must retain the above copyright
18
//       notice, this list of conditions and the following disclaimer.
19
//     * Redistributions in binary form must reproduce the above copyright
20
//       notice, this list of conditions and the following disclaimer in the
21
//       documentation and/or other materials provided with the distribution.
22
//     * Neither the name of the  nor the
23
//       names of its contributors may be used to endorse or promote products
24
//       derived from this software without specific prior written permission.
25
//
26
// THIS SOFTWARE IS PROVIDED BY Robert Hayes ''AS IS'' AND ANY
27
// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
28
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
29
// DISCLAIMED. IN NO EVENT SHALL Robert Hayes BE LIABLE FOR ANY
30
// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
31
// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
32
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
33
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
35
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36
////////////////////////////////////////////////////////////////////////////////
37
// 45678901234567890123456789012345678901234567890123456789012345678901234567890
38
 
39
 
40
`include "timescale.v"
41
 
42
module tst_bench_top();
43
 
44
  parameter STOP_ON_ERROR = 1'b0;
45
  parameter MAX_VECTOR = 1_000;
46
  //
47
  // wires && regs
48
  //
49
  logic        mstr_test_clk;
50
  logic [19:0] vector;
51
  logic [ 7:0] test_num;
52
  logic        rstn;
53
  logic        sync_reset;
54
 
55
  logic [31:0] adr;
56
  logic [15:0] dat_i, dat_o, dat0_i, dat1_i, dat2_i, dat3_i;
57
  logic we;
58
  logic stb;
59
  logic cyc;
60
  logic ack, ack_1, ack_2, ack_3, ack_4;
61
  logic inta_1, inta_2, inta_3, inta_4;
62
  logic count_en_1;
63
  logic count_flag_1;
64
 
65
  logic [15:0] q, qq;
66
  logic [15:0] error_count;
67
 
68
  logic scl, scl0_o, scl0_oen, scl1_o, scl1_oen;
69
  logic sda, sda0_o, sda0_oen, sda1_o, sda1_oen;
70
 
71
  // Name Address Locations
72
  parameter PIT_CNTRL = 5'b0_0000;
73
  parameter PIT_MOD   = 5'b0_0001;
74
  parameter PIT_COUNT = 5'b0_0010;
75
 
76
  parameter RD      = 1'b1;
77
  parameter WR      = 1'b0;
78
  parameter SADR    = 7'b0010_000;
79
 
80
  parameter CTR_EN  = 8'b1000_0000;  // core enable bit
81
  parameter CTR_IEN = 8'b0100_0000;  // core interrupt enable bit
82
 
83
  parameter PIT_CNTRL_SLAVE  = 16'h8000;  // PIT Slave mode
84
  parameter PIT_CNTRL_FLAG   = 16'h0004;  // PIT Rollover Flag
85
  parameter PIT_CNTRL_IRQEN  = 16'h0002;  // PIT Interupt Enable
86
  parameter PIT_CNTRL_ENA    = 16'h0001;  // PIT Enable
87
 
88
  parameter SLAVE_0_CNTRL = 5'b0_1000;
89
  parameter SLAVE_0_MOD   = 5'b0_1001;
90
  parameter SLAVE_0_COUNT = 5'b0_1010;
91
 
92
  parameter SLAVE_1_CNTRL = 5'b1_0000;
93
  parameter SLAVE_1_MOD   = 5'b1_0001;
94
  parameter SLAVE_1_COUNT = 5'b1_0010;
95
 
96
  parameter SLAVE_2_CNTRL_0 = 5'b1_1000;
97
  parameter SLAVE_2_CNTRL_1 = 5'b1_1001;
98
  parameter SLAVE_2_MOD_0   = 5'b1_1010;
99
  parameter SLAVE_2_MOD_1   = 5'b1_1011;
100
  parameter SLAVE_2_COUNT_0 = 5'b1_1100;
101
  parameter SLAVE_2_COUNT_1 = 5'b1_1101;
102
 
103
  // initial values and testbench setup
104
  initial
105
    begin
106
      mstr_test_clk = 0;
107
      vector = 0;
108
      test_num = 0;
109
      error_count = 0;
110
 
111
      `ifdef WAVES
112
           $shm_open("waves");
113
           $shm_probe("AS",tst_bench_top,"AS");
114
           $display("\nINFO: Signal dump enabled ...\n\n");
115
      `endif
116
 
117
      `ifdef WAVES_V
118
           $dumpfile ("pit_wave_dump.lxt");
119
           $dumpvars (0, tst_bench_top);
120
           $dumpon;
121
           $display("\nINFO: VCD Signal dump enabled ...\n\n");
122
      `endif
123
 
124
      `ifdef DEBUSSY
125
           $fsdbDumpfile("pit_wave_dump.fsdb");
126
           $fsdbDumpvars(0);
127
           $display("\nINFO: Debussy Signal dump enabled ...\n\n");
128
      `endif
129
 
130
    end
131
 
132
  // generate clock
133
  always #20 mstr_test_clk = ~mstr_test_clk;
134
 
135
  // Keep a count of how many clocks we've simulated
136
  always @(posedge mstr_test_clk)
137
    begin
138
      vector <= vector + 1;
139
      if (vector > MAX_VECTOR)
140
        begin
141
          error_count <= error_count + 1;
142
          $display("\n ------ !!!!! Simulation Timeout at vector=%d\n -------", vector);
143
          wrap_up;
144
        end
145
    end
146
 
147
  // Add up errors tha come from WISHBONE read compares
148
  always @u0.cmp_error_detect
149
    begin
150
      error_count <= error_count + 1;
151
    end
152
 
153
  // hookup wishbone master model
154
  wb_master_model #(.dwidth(16), .awidth(32))
155
          u0 (
156
          .clk(mstr_test_clk),
157
          .rst(rstn),
158
          .adr(adr),
159
          .din(dat_i),
160
          .dout(dat_o),
161
          .cyc(cyc),
162
          .stb(stb),
163
          .we(we),
164
          .sel(),
165
          .ack(ack),
166
          .err(1'b0),
167
          .rty(1'b0)
168
  );
169
 
170
 
171
  // Address decoding for different PIT module instances
172
  wire stb0 = stb && ~adr[4] && ~adr[3];
173
  wire stb1 = stb && ~adr[4] &&  adr[3];
174
  wire stb2 = stb &&  adr[4] && ~adr[3];
175
  wire stb3 = stb &&  adr[4] &&  adr[3];
176
 
177
  // Create the Read Data Bus
178
  assign dat_i = ({16{stb0}} & dat0_i) |
179
                 ({16{stb1}} & dat1_i) |
180
                 ({16{stb2}} & dat2_i) |
181
                 ({16{stb3}} & {8'b0, dat3_i[7:0]});
182
 
183
  assign ack = ack_1 || ack_2 || ack_3 || ack_4;
184
 
185
  // hookup wishbone_PIT_master core - Parameters take all default values
186
  //  Async Reset, 16 bit Bus, 16 bit Granularity,Wait States
187
  pit_top #(.SINGLE_CYCLE(1'b0))
188
          pit_1(
189
          // wishbone interface
190
          .wb_clk_i(mstr_test_clk),
191
          .wb_rst_i(1'b0),
192
          .arst_i(rstn),
193
          .wb_adr_i(adr[2:0]),
194
          .wb_dat_i(dat_o),
195
          .wb_dat_o(dat0_i),
196
          .wb_we_i(we),
197
          .wb_stb_i(stb0),
198
          .wb_cyc_i(cyc),
199
          .wb_sel_i( 2'b11 ),
200
          .wb_ack_o(ack_1),
201
          .pit_irq_o(inta_1),
202
 
203
          .pit_o(pit_1_out),
204
          .ext_sync_i(1'b0),
205
          .cnt_sync_o(count_en_1),
206
          .cnt_flag_o(count_flag_1)
207
  );
208
 
209
  // hookup wishbone_PIT_slave core - Parameters take all default values
210
  //  Sync Reset, 16 bit Bus, 16 bit Granularity
211
  pit_top #(.ARST_LVL(1'b1))
212
          pit_2(
213
          // wishbone interface
214
          .wb_clk_i(mstr_test_clk),
215
          .wb_rst_i(sync_reset),
216
          .arst_i(1'b0),
217
          .wb_adr_i(adr[2:0]),
218
          .wb_dat_i(dat_o),
219
          .wb_dat_o(dat1_i),
220
          .wb_we_i(we),
221
          .wb_stb_i(stb1),
222
          .wb_cyc_i(cyc),
223
          .wb_sel_i( 2'b11 ),
224
          .wb_ack_o(ack_2),
225
          .pit_irq_o(inta_2),
226
 
227
          .pit_o(pit_2_out),
228
          .ext_sync_i(count_en_1),
229
          .cnt_sync_o(count_en_2),
230
          .cnt_flag_o(count_flag_2)
231
  );
232
 
233
  // hookup wishbone_PIT_slave core
234
  //  16 bit Bus, 16 bit Granularity
235
  pit_top #(.NO_PRESCALE(1'b1))
236
          pit_3(
237
          // wishbone interface
238
          .wb_clk_i(mstr_test_clk),
239
          .wb_rst_i(sync_reset),
240
          .arst_i(1'b1),
241
          .wb_adr_i(adr[2:0]),
242
          .wb_dat_i(dat_o),
243
          .wb_dat_o(dat2_i),
244
          .wb_we_i(we),
245
          .wb_stb_i(stb2),
246
          .wb_cyc_i(cyc),
247
          .wb_sel_i( 2'b11 ),
248
          .wb_ack_o(ack_3),
249
          .pit_irq_o(inta_3),
250
 
251
          .pit_o(pit_3_out),
252
          .ext_sync_i(count_en_1),
253
          .cnt_sync_o(count_en_3),
254
          .cnt_flag_o(count_flag_3)
255
  );
256
 
257
  // hookup wishbone_PIT_slave core
258
  //  8 bit Bus, 8 bit Granularity
259
  pit_top #(.DWIDTH(8))
260
          pit_4(
261
          // wishbone interface
262
          .wb_clk_i(mstr_test_clk),
263
          .wb_rst_i(sync_reset),
264
          .arst_i(1'b1),
265
          .wb_adr_i(adr[2:0]),
266
          .wb_dat_i(dat_o[7:0]),
267
          .wb_dat_o(dat3_i[7:0]),
268
          .wb_we_i(we),
269
          .wb_stb_i(stb3),
270
          .wb_cyc_i(cyc),
271
          .wb_sel_i( 2'b11 ),
272
          .wb_ack_o(ack_4),
273
          .pit_irq_o(inta_4),
274
 
275
          .pit_o(pit_4_out),
276
          .ext_sync_i(count_en_1),
277
          .cnt_sync_o(count_en_4),
278
          .cnt_flag_o(count_flag_4)
279
  );
280
 
281
// Test Program
282
initial
283
  begin
284
      $display("\nstatus: %t Testbench started", $time);
285
 
286
      // reset system
287
      rstn = 1'b1; // negate reset
288
      repeat(1) @(posedge mstr_test_clk);
289
      sync_reset = 1'b1;  // Make the sync reset 1 clock cycle long
290
      #2;          // move the async reset away from the clock edge
291
      rstn = 1'b0; // assert async reset
292
      #5;          // Keep the async reset pulse with less than a clock cycle
293
      rstn = 1'b1; // negate async reset
294
      repeat(1) @(posedge mstr_test_clk);
295
      sync_reset = 1'b0;
296
 
297
      $display("\nstatus: %t done reset", $time);
298
      test_num = test_num + 1;
299
 
300
      repeat(2) @(posedge mstr_test_clk);
301
 
302
      //
303
      // program core
304
      //
305
 
306
      reg_test_16;
307
 
308
      reg_test_8;
309
 
310
      u0.wb_write(1, SLAVE_0_CNTRL,   PIT_CNTRL_SLAVE); // Enable Slave Mode
311
      u0.wb_write(1, SLAVE_1_CNTRL,   PIT_CNTRL_SLAVE); // Enable Slave Mode
312
      u0.wb_write(1, SLAVE_2_CNTRL_1, 16'h0080); // Enable Slave Mode
313
      u0.wb_write(1, SLAVE_0_MOD,     16'h000a); // load Modulo
314
      u0.wb_write(1, SLAVE_1_MOD,     16'h0010); // load Modulo
315
      u0.wb_write(1, SLAVE_2_MOD_0,   16'h0010); // load Modulo
316
 
317
      // Set Master Mode PS=0, Modulo=16
318
      test_num = test_num + 1;
319
      $display("TEST #%d Starts at vector=%d, ms_test", test_num, vector);
320
 
321
      u0.wb_write(1, PIT_MOD,   16'h0010); // load prescaler hi-byte
322
      u0.wb_write(1, PIT_CNTRL, PIT_CNTRL_ENA); // Enable to start counting
323
      $display("status: %t programmed registers", $time);
324
 
325
      wait_flag_set;  // Wait for Counter to tomeout
326
      u0.wb_write(1, PIT_CNTRL, PIT_CNTRL_FLAG | PIT_CNTRL_ENA); //
327
 
328
      wait_flag_set;  // Wait for Counter to tomeout
329
      u0.wb_write(1, PIT_CNTRL, PIT_CNTRL_FLAG | PIT_CNTRL_ENA); //
330
 
331
      repeat(10) @(posedge mstr_test_clk);
332
      u0.wb_write(1, PIT_CNTRL, 16'b0); //
333
 
334
      repeat(10) @(posedge mstr_test_clk);
335
 
336
      mstr_psx_modx(2,4);
337
 
338
      mstr_psx_modx(4,0);
339
 
340
      repeat(100) @(posedge mstr_test_clk);
341
 
342
      wrap_up;
343
 
344
  end  // Main Test Flow
345
 
346
// Poll for flag set
347
task wait_flag_set;
348
  u0.wb_read(1, PIT_CNTRL, q);
349
  while(~|(q & PIT_CNTRL_FLAG))
350
    u0.wb_read(1, PIT_CNTRL, q); // poll it until it is set
351
  $display("PIT Flag set detected at vector =%d", vector);
352
endtask
353
 
354
// check register bits - reset, read/write
355
task reg_test_16;
356
  test_num = test_num + 1;
357
  $display("TEST #%d Starts at vector=%d, reg_test_16", test_num, vector);
358
  u0.wb_cmp(0, PIT_CNTRL, 16'h4000);   // verify reset
359
  u0.wb_cmp(0, PIT_MOD,   16'h0000);   // verify reset
360
  u0.wb_cmp(0, PIT_COUNT, 16'h0001);   // verify reset
361
 
362
  u0.wb_write(1, PIT_CNTRL, 16'hfffe); // load prescaler lo-byte
363
  u0.wb_cmp(  0, PIT_CNTRL, 16'hCf02); // verify write data
364
  u0.wb_write(1, PIT_CNTRL, 16'h0000); // load prescaler lo-byte
365
  u0.wb_cmp(  0, PIT_CNTRL, 16'h4000); // verify write data
366
 
367
  u0.wb_write(1, PIT_MOD, 16'h5555); // load prescaler lo-byte
368
  u0.wb_cmp(  0, PIT_MOD, 16'h5555); // verify write data
369
  u0.wb_write(1, PIT_MOD, 16'haaaa); // load prescaler lo-byte
370
  u0.wb_cmp(  0, PIT_MOD, 16'haaaa); // verify write data
371
 
372
  u0.wb_write(0, PIT_COUNT, 16'hfffe);
373
  u0.wb_cmp(  0, PIT_COUNT, 16'h0001); // verify register not writable
374
endtask
375
 
376
task reg_test_8;
377
  test_num = test_num + 1;
378
  $display("TEST #%d Starts at vector=%d, reg_test_8", test_num, vector);
379
  u0.wb_cmp(0, SLAVE_2_CNTRL_0, 16'h0000);   // verify reset
380
  u0.wb_cmp(0, SLAVE_2_CNTRL_1, 16'h0040);   // verify reset
381
  u0.wb_cmp(0, SLAVE_2_MOD_0,   16'h0000);   // verify reset
382
  u0.wb_cmp(0, SLAVE_2_MOD_1,   16'h0000);   // verify reset
383
  u0.wb_cmp(0, SLAVE_2_COUNT_0, 16'h0001);   // verify reset
384
  u0.wb_cmp(0, SLAVE_2_COUNT_1, 16'h0000);   // verify reset
385
 
386
  u0.wb_write(1, SLAVE_2_CNTRL_0, 16'hfffe); // load prescaler lo-byte
387
  u0.wb_cmp(  0, SLAVE_2_CNTRL_0, 16'h0002); // verify write data
388
  u0.wb_write(1, SLAVE_2_CNTRL_0, 16'h0000); // load prescaler lo-byte
389
  u0.wb_cmp(  0, SLAVE_2_CNTRL_0, 16'h0000); // verify write data
390
  u0.wb_cmp(  0, SLAVE_2_CNTRL_1, 16'h0040); // verify write data
391
 
392
  u0.wb_write(1, SLAVE_2_MOD_0, 16'hff55); // load prescaler lo-byte
393
  u0.wb_cmp(  0, SLAVE_2_MOD_0, 16'h0055); // verify write data
394
  u0.wb_write(1, SLAVE_2_MOD_0, 16'hffaa); // load prescaler lo-byte
395
  u0.wb_cmp(  0, SLAVE_2_MOD_0, 16'h00aa); // verify write data
396
  u0.wb_write(1, SLAVE_2_MOD_1, 16'hff66); // load prescaler lo-byte
397
  u0.wb_cmp(  0, SLAVE_2_MOD_1, 16'h0066); // verify write data
398
  u0.wb_write(1, SLAVE_2_MOD_1, 16'hff99); // load prescaler lo-byte
399
  u0.wb_cmp(  0, SLAVE_2_MOD_1, 16'h0099); // verify write data
400
  u0.wb_write(1, SLAVE_2_MOD_1, 16'hff00); // load prescaler lo-byte
401
 
402
  u0.wb_write(0, SLAVE_2_COUNT_0, 16'hfffe);
403
  u0.wb_cmp(  0, SLAVE_2_COUNT_0, 16'h0001); // verify register not writable
404
  u0.wb_write(0, SLAVE_2_COUNT_1, 16'hfffe);
405
  u0.wb_cmp(  0, SLAVE_2_COUNT_1, 16'h0000); // verify register not writable
406
endtask
407
 
408
task mstr_psx_modx(
409
  logic [ 3:0] ps_val,
410
  logic [15:0] mod_val);
411
  logic [15:0] cntrl_val;
412
  test_num = test_num + 1;
413
  $display("TEST #%d Starts at vector=%d, mstr_psx_modx Pre=%h, Mod=%h",
414
          test_num, vector, ps_val, mod_val);
415
  // program internal registers
416
 
417
  cntrl_val = {1'b0, 3'b0, ps_val, 8'b0} | PIT_CNTRL_IRQEN;
418
  u0.wb_write(1, PIT_MOD,   mod_val); // load modulo
419
  u0.wb_write(1, PIT_CNTRL, ( cntrl_val | PIT_CNTRL_ENA)); // Enable to start counting
420
 
421
  wait_flag_set;  // Wait for Counter to timeout
422
  u0.wb_write(1, PIT_CNTRL, cntrl_val | PIT_CNTRL_FLAG | PIT_CNTRL_ENA); //
423
 
424
  wait_flag_set;  // Wait for Counter to timeout
425
  u0.wb_write(1, PIT_CNTRL, cntrl_val | PIT_CNTRL_FLAG | PIT_CNTRL_ENA); //
426
 
427
  repeat(10) @(posedge mstr_test_clk);
428
 
429
  u0.wb_write(1, PIT_CNTRL, 16'b0); //
430
endtask
431
 
432
task wrap_up;
433
  test_num = test_num + 1;
434
  repeat(10) @(posedge mstr_test_clk);
435
  $display("\nSimulation Finished!! - vector =%d", vector);
436
  if (error_count == 0)
437
  $display("Simulation Passed");
438
  else
439
  $display("Simulation Failed  --- Errors =%d", error_count);
440
 
441
  $finish;
442
endtask
443
 
444
 
445
endmodule  // tst_bench_top
446
 

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