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1 24 rehayes
////////////////////////////////////////////////////////////////////////////////
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//
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//  WISHBONE rev.B2 Wishbone Master model
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//
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//  Author: Bob Hayes
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//          rehayes@opencores.org
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//
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//  Downloaded from: http://www.opencores.org/projects/pit.....
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//
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////////////////////////////////////////////////////////////////////////////////
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// Copyright (c) 2011, Robert Hayes
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//     * Redistributions of source code must retain the above copyright
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//       notice, this list of conditions and the following disclaimer.
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//     * Redistributions in binary form must reproduce the above copyright
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//       notice, this list of conditions and the following disclaimer in the
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//       documentation and/or other materials provided with the distribution.
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//     * Neither the name of the  nor the
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//       names of its contributors may be used to endorse or promote products
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//       derived from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY Robert Hayes ''AS IS'' AND ANY
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// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL Robert Hayes BE LIABLE FOR ANY
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// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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////////////////////////////////////////////////////////////////////////////////
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// 45678901234567890123456789012345678901234567890123456789012345678901234567890
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`include "timescale.v"
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module wb_master_model  #(parameter dwidth = 32,
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                          parameter awidth = 32)
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(
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  // Wishbone Signals
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wishbone_if.master           wb_1,          // Define the interface instance name
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wishbone_if.master           wb_2,          // Define the interface instance name
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wishbone_if.master           wb_3,          // Define the interface instance name
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wishbone_if.master           wb_4,          // Define the interface instance name
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output logic                 cyc,
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output logic                 stb,
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output logic                 we,
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output logic [dwidth/8 -1:0] sel,
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output logic [awidth   -1:0] adr,
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output logic [dwidth   -1:0] dout,
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input  logic [dwidth   -1:0] din,
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input  logic                 clk,
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input  logic                 ack,
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input  logic                 rst,  // No Connect
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input  logic                 err,  // No Connect
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input  logic                 rty   // No Connect
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);
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//////////////////////////////////
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//
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// Local Wires
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//
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logic [dwidth-1:0] q;
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event cmp_error_detect;
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assign wb_1.wb_adr = adr[2:0];
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assign wb_1.wb_sel = 2'b11;
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assign wb_1.wb_we  = we;
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assign wb_1.wb_cyc = cyc;
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assign wb_1.wb_dat = dout;
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assign wb_2.wb_adr = adr[2:0];
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assign wb_2.wb_sel = 2'b11;
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assign wb_2.wb_we  = we;
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assign wb_2.wb_cyc = cyc;
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assign wb_2.wb_dat = dout;
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assign wb_3.wb_adr = adr[2:0];
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assign wb_3.wb_sel = 2'b11;
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assign wb_3.wb_we  = we;
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assign wb_3.wb_cyc = cyc;
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assign wb_3.wb_dat = dout;
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assign wb_4.wb_adr = adr[2:0];
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assign wb_4.wb_sel = 2'b11;
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assign wb_4.wb_we  = we;
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assign wb_4.wb_cyc = cyc;
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assign wb_4.wb_dat = dout[7:0];
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//////////////////////////////////
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//
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// Memory Logic
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//
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initial
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  begin
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    adr  <= 'x;
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    dout <= 'x;
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    cyc  <= 1'b0;
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    stb  <= 1'bx;
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    we   <= 1'hx;
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    sel  <= 'x;
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    #1;
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    $display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)");
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  end
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//////////////////////////////////
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//
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// Wishbone write cycle
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//
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task wb_write(
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  integer delay,
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  logic   [awidth -1:0] a,
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  logic   [dwidth -1:0] d);
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  // wait initial delay
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  repeat(delay) @(posedge clk);
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  // assert wishbone signal
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  #1;
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  adr  = a;
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  dout = d;
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  cyc  = 1'b1;
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  stb  = 1'b1;
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  we   = 1'b1;
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  sel  = '1;
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  @(posedge clk);
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  // wait for acknowledge from slave
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  while(~ack)     @(posedge clk);
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  // negate wishbone signals
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  #1;
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  cyc  = 1'b0;
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  stb  = 1'bx;
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  adr  = 'x;
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  dout = 'x;
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  we   = 1'hx;
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  sel  = 'x;
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endtask
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//////////////////////////////////
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//
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// Wishbone read cycle
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//
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task wb_read(
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  integer delay,
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  logic         [awidth -1:0] a,
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  output logic  [dwidth -1:0] d);
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  // wait initial delay
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  repeat(delay) @(posedge clk);
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  // assert wishbone signals
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  #1;
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  adr  = a;
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  dout = 'x;
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  cyc  = 1'b1;
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  stb  = 1'b1;
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  we   = 1'b0;
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  sel  = '1;
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  @(posedge clk);
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  // wait for acknowledge from slave
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  while(~ack)     @(posedge clk);
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  // negate wishbone signals
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  d    = din; // Grab the data on the posedge of clock
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  #1;         // Delay the clearing (hold time of the control signals
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  cyc  = 1'b0;
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  stb  = 1'bx;
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  adr  = 'x;
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  dout = 'x;
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  we   = 1'hx;
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  sel  = 'x;
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  d    = din;
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endtask
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//////////////////////////////////
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//
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// Wishbone compare cycle (read data from location and compare with expected data)
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//
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task wb_cmp(
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  integer delay,
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  logic [awidth -1:0] a,
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  logic [dwidth -1:0] d_exp);
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  wb_read (delay, a, q);
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  if (d_exp !== q)
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    begin
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      -> cmp_error_detect;
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      $display("Data compare error at address %h. Received %h, expected %h at time %t", a, q, d_exp, $time);
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    end
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endtask
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endmodule : wb_master_model
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