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///////////////////////////////////////////////////////////////////////
////                                                               ////
////  WISHBONE rev.B2 Wishbone Master model                        ////
////                                                               ////
////                                                               ////
////  Author: Richard Herveille                                    ////
////          richard@asics.ws                                     ////
////          www.asics.ws                                         ////
////                                                               ////
////  Downloaded from: http://www.opencores.org/projects/mem_ctrl  ////
////                                                               ////
///////////////////////////////////////////////////////////////////////
////                                                               ////
//// Copyright (C) 2001 Richard Herveille                          ////
////                    richard@asics.ws                           ////
////                                                               ////
//// This source file may be used and distributed without          ////
//// restriction provided that this copyright statement is not     ////
//// removed from the file and that any derivative work contains   ////
//// the original copyright notice and the associated disclaimer.  ////
////                                                               ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY       ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED     ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS     ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR        ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,           ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES      ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE     ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR          ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT    ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT    ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE           ////
//// POSSIBILITY OF SUCH DAMAGE.                                   ////
////                                                               ////
///////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: wb_master_model.v,v 1.4 2004/02/28 15:40:42 rherveille Exp $
//
//  $Date: 2004/02/28 15:40:42 $
//  $Revision: 1.4 $
//  $Author: rherveille $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//
`include "timescale.v"
 
module wb_master_model  #(parameter dwidth = 32,
                          parameter awidth = 32)
(
output logic                 cyc,
output logic                 stb,
output logic                 we,
output logic [dwidth/8 -1:0] sel,
output logic [awidth   -1:0] adr,
output logic [dwidth   -1:0] dout,
input  logic [dwidth   -1:0] din,
input  logic                 clk,
input  logic                 ack,
input  logic                 rst,  // No Connect
input  logic                 err,  // No Connect
input  logic                 rty   // No Connect
);
 
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
 
 
logic [dwidth   -1:0] q;
 
event cmp_error_detect;
 
////////////////////////////////////////////////////////////////////
//
// Memory Logic
//
 
initial
  begin
    adr  = 'x;
    dout = 'x;
    cyc  = 1'b0;
    stb  = 1'bx;
    we   = 1'hx;
    sel  = 'x;
    #1;
    $display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)");
  end
 
////////////////////////////////////////////////////////////////////
//
// Wishbone write cycle
//
 
task wb_write(
  integer delay,
  logic   [awidth -1:0] a,
  logic   [dwidth -1:0] d);
 
  // wait initial delay
  repeat(delay) @(posedge clk);
 
  // assert wishbone signal
  #1;
  adr  = a;
  dout = d;
  cyc  = 1'b1;
  stb  = 1'b1;
  we   = 1'b1;
  sel  = '1;
  @(posedge clk);
 
  // wait for acknowledge from slave
  while(~ack)     @(posedge clk);
 
  // negate wishbone signals
  #1;
  cyc  = 1'b0;
  stb  = 1'bx;
  adr  = 'x;
  dout = 'x;
  we   = 1'hx;
  sel  = 'x;
 
endtask
 
////////////////////////////////////////////////////////////////////
//
// Wishbone read cycle
//
 
task wb_read(
  integer delay,
  logic         [awidth -1:0] a,
  output logic  [dwidth -1:0] d);
 
  // wait initial delay
  repeat(delay) @(posedge clk);
 
  // assert wishbone signals
  #1;
  adr  = a;
  dout = 'x;
  cyc  = 1'b1;
  stb  = 1'b1;
  we   = 1'b0;
  sel  = '1;
  @(posedge clk);
 
  // wait for acknowledge from slave
  while(~ack)     @(posedge clk);
 
  // negate wishbone signals
  d    = din; // Grab the data on the posedge of clock
  #1;         // Delay the clearing (hold time of the control signals
  cyc  = 1'b0;
  stb  = 1'bx;
  adr  = 'x;
  dout = 'x;
  we   = 1'hx;
  sel  = 'x;
  d    = din;
 
endtask
 
////////////////////////////////////////////////////////////////////
//
// Wishbone compare cycle (read data from location and compare with expected data)
//
 
task wb_cmp(
  integer delay,
  logic [awidth -1:0] a,
  logic [dwidth -1:0] d_exp);
 
  wb_read (delay, a, q);
 
  if (d_exp !== q)
    begin
      -> cmp_error_detect;
      $display("Data compare error at address %h. Received %h, expected %h at time %t", a, q, d_exp, $time);
    end
endtask
 
endmodule
 
 

Line No.	Rev	Author	Line
1	23	rehayes	`///////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE rev.B2 Wishbone Master model ////`
4			`//// ////`
5			`//// ////`
6			`//// Author: Richard Herveille ////`
7			`//// richard@asics.ws ////`
8			`//// www.asics.ws ////`
9			`//// ////`
10			`//// Downloaded from: http://www.opencores.org/projects/mem_ctrl ////`
11			`//// ////`
12			`///////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2001 Richard Herveille ////`
15			`//// richard@asics.ws ////`
16			`//// ////`
17			`//// This source file may be used and distributed without ////`
18			`//// restriction provided that this copyright statement is not ////`
19			`//// removed from the file and that any derivative work contains ////`
20			`//// the original copyright notice and the associated disclaimer. ////`
21			`//// ////`
22			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
23			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
24			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
25			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
26			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
27			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
28			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
29			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
30			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
31			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
32			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
33			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
34			`//// POSSIBILITY OF SUCH DAMAGE. ////`
35			`//// ////`
36			`///////////////////////////////////////////////////////////////////////`
37
38			`// CVS Log`
39			`//`
40			`// $Id: wb_master_model.v,v 1.4 2004/02/28 15:40:42 rherveille Exp $`
41			`//`
42			`// $Date: 2004/02/28 15:40:42 $`
43			`// $Revision: 1.4 $`
44			`// $Author: rherveille $`
45			`// $Locker: $`
46			`// $State: Exp $`
47			`//`
48			`// Change History:`
49			`//`
50			`include "timescale.v"
51
52			`module wb_master_model #(parameter dwidth = 32,`
53			`parameter awidth = 32)`
54			`(`
55			`output logic cyc,`
56			`output logic stb,`
57			`output logic we,`
58			`output logic [dwidth/8 -1:0] sel,`
59			`output logic [awidth -1:0] adr,`
60			`output logic [dwidth -1:0] dout,`
61			`input logic [dwidth -1:0] din,`
62			`input logic clk,`
63			`input logic ack,`
64			`input logic rst, // No Connect`
65			`input logic err, // No Connect`
66			`input logic rty // No Connect`
67			`);`
68
69			`////////////////////////////////////////////////////////////////////`
70			`//`
71			`// Local Wires`
72			`//`
73
74
75			`logic [dwidth -1:0] q;`
76
77			`event cmp_error_detect;`
78
79			`////////////////////////////////////////////////////////////////////`
80			`//`
81			`// Memory Logic`
82			`//`
83
84			`initial`
85			`begin`
86			`adr = 'x;`
87			`dout = 'x;`
88			`cyc = 1'b0;`
89			`stb = 1'bx;`
90			`we = 1'hx;`
91			`sel = 'x;`
92			`#1;`
93			`$display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)");`
94			`end`
95
96			`////////////////////////////////////////////////////////////////////`
97			`//`
98			`// Wishbone write cycle`
99			`//`
100
101			`task wb_write(`
102			`integer delay,`
103			`logic [awidth -1:0] a,`
104			`logic [dwidth -1:0] d);`
105
106			`// wait initial delay`
107			`repeat(delay) @(posedge clk);`
108
109			`// assert wishbone signal`
110			`#1;`
111			`adr = a;`
112			`dout = d;`
113			`cyc = 1'b1;`
114			`stb = 1'b1;`
115			`we = 1'b1;`
116			`sel = '1;`
117			`@(posedge clk);`
118
119			`// wait for acknowledge from slave`
120			`while(~ack) @(posedge clk);`
121
122			`// negate wishbone signals`
123			`#1;`
124			`cyc = 1'b0;`
125			`stb = 1'bx;`
126			`adr = 'x;`
127			`dout = 'x;`
128			`we = 1'hx;`
129			`sel = 'x;`
130
131			`endtask`
132
133			`////////////////////////////////////////////////////////////////////`
134			`//`
135			`// Wishbone read cycle`
136			`//`
137
138			`task wb_read(`
139			`integer delay,`
140			`logic [awidth -1:0] a,`
141			`output logic [dwidth -1:0] d);`
142
143			`// wait initial delay`
144			`repeat(delay) @(posedge clk);`
145
146			`// assert wishbone signals`
147			`#1;`
148			`adr = a;`
149			`dout = 'x;`
150			`cyc = 1'b1;`
151			`stb = 1'b1;`
152			`we = 1'b0;`
153			`sel = '1;`
154			`@(posedge clk);`
155
156			`// wait for acknowledge from slave`
157			`while(~ack) @(posedge clk);`
158
159			`// negate wishbone signals`
160			`d = din; // Grab the data on the posedge of clock`
161			`#1; // Delay the clearing (hold time of the control signals`
162			`cyc = 1'b0;`
163			`stb = 1'bx;`
164			`adr = 'x;`
165			`dout = 'x;`
166			`we = 1'hx;`
167			`sel = 'x;`
168			`d = din;`
169
170			`endtask`
171
172			`////////////////////////////////////////////////////////////////////`
173			`//`
174			`// Wishbone compare cycle (read data from location and compare with expected data)`
175			`//`
176
177			`task wb_cmp(`
178			`integer delay,`
179			`logic [awidth -1:0] a,`
180			`logic [dwidth -1:0] d_exp);`
181
182			`wb_read (delay, a, q);`
183
184			`if (d_exp !== q)`
185			`begin`
186			`-> cmp_error_detect;`
187			`$display("Data compare error at address %h. Received %h, expected %h at time %t", a, q, d_exp, $time);`
188			`end`
189			`endtask`
190
191			`endmodule`
192
193

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[/] [pit/] [trunk/] [bench/] [sys_verilog/] [wb_master_model.sv] - Blame information for rev 23