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rehayes |
////////////////////////////////////////////////////////////////////////////////
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//
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// Programable Interrupt Timer - Main Counter
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//
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// Author: Bob Hayes
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// rehayes@opencores.org
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//
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// Downloaded from: http://www.opencores.org/projects/pit.....
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//
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////////////////////////////////////////////////////////////////////////////////
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// Copyright (c) 2011, Robert Hayes
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// * Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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// * Neither the name of the nor the
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// names of its contributors may be used to endorse or promote products
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// derived from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY Robert Hayes ''AS IS'' AND ANY
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// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL Robert Hayes BE LIABLE FOR ANY
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// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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////////////////////////////////////////////////////////////////////////////////
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// 45678901234567890123456789012345678901234567890123456789012345678901234567890
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module pit_count #(parameter COUNT_SIZE = 16)
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(
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output logic [COUNT_SIZE-1:0] cnt_n, // Modulo Counter value
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output logic cnt_flag_o, // Counter Rollover Flag
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output logic pit_o, // PIT output pulse
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input async_rst_b, //
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input sync_reset, // Syncronous reset signal
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input bus_clk, // Reference Clock
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input counter_sync, // Syncronous counter enable
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input prescale_out, // Increment Counter
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input pit_flg_clr, // Clear PIT Rollover Flag
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input [COUNT_SIZE-1:0] mod_value // Count Divisor
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);
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// Warning: This counter has no saftynet if the mod_value changes while the counter
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// is active. There may need to be an addtional latch register for
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// "mod_value" that captures on the falling edge of "counter_sync" or
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// when "cnt_n" rolls over to eliminate this problem.
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logic rollover; // Counter has reached the mod_value
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logic no_div; // Modulo set for Zero or One
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logic clear_counter; // Set counter to initial state
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assign no_div = (mod_value == 1) || ~|mod_value;
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assign rollover = ((cnt_n == mod_value) || no_div) && prescale_out;
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assign clear_counter = !counter_sync;
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// Div N Counter
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always @(posedge bus_clk or negedge async_rst_b)
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if ( !async_rst_b )
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cnt_n <= 1;
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else if ( clear_counter || rollover || no_div)
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cnt_n <= 1;
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else if ( prescale_out )
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cnt_n <= cnt_n + 1;
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// Counter Rollover Flag and Interrupt
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always @(posedge bus_clk or negedge async_rst_b)
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if ( !async_rst_b )
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cnt_flag_o <= 0;
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else if ( clear_counter || pit_flg_clr)
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cnt_flag_o <= 0;
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else if ( rollover )
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cnt_flag_o <= 1;
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// PIT Output Register
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always @(posedge bus_clk or negedge async_rst_b)
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if ( !async_rst_b )
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pit_o <= 0;
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else
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pit_o <= rollover && counter_sync && !sync_reset;
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endmodule // pit_count
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