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rehayes |
////////////////////////////////////////////////////////////////////////////////
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//
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// WISHBONE revB.2 compliant Programable Interrupt Timer - Control registers
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//
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// Author: Bob Hayes
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// rehayes@opencores.org
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//
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// Downloaded from: http://www.opencores.org/projects/pit.....
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//
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////////////////////////////////////////////////////////////////////////////////
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// Copyright (c) 2011, Robert Hayes
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// * Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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// * Neither the name of the nor the
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// names of its contributors may be used to endorse or promote products
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// derived from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY Robert Hayes ''AS IS'' AND ANY
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// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL Robert Hayes BE LIABLE FOR ANY
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// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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////////////////////////////////////////////////////////////////////////////////
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// 45678901234567890123456789012345678901234567890123456789012345678901234567890
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module pit_regs #(parameter COUNT_SIZE = 16,
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parameter NO_PRESCALE = 1'b0,
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parameter DWIDTH = 16)
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(
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output logic [COUNT_SIZE-1:0] mod_value, // Main Counter Modulo Value
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output [ 3:0] pit_pre_scl, // PIT Prescaler Value
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output logic pit_slave, // PIT Slave Mode
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output logic pit_flg_clr, // Clear PIT Rollover Flag
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output logic pit_ien, // PIT Interrupt Enable
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output logic cnt_sync_o, // PIT Counter Enable
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output logic pit_irq_o, // PIT interrupt
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input bus_clk, // Control register bus clock
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input async_rst_b, // Async reset signal
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input sync_reset, // Syncronous reset signal
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input pit_flag, // PIT Rollover Flag
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input [DWIDTH-1:0] write_bus, // Write Data Bus
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input [ 3:0] write_regs, // Write Register strobes
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input cnt_flag_o // Counter Rollover Flag
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);
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// registers
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logic [ 3:0] pit_pre; // Optional register for PIT Prescale Counter modulo
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// This register should be removed durning synthesis
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// if the "NO_PRESCALE" parameter is set
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// Wires
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logic [15:0] write_data; // Data bus mux for 8 or 16 bit module bus
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//
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// module body
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//
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assign write_data = (DWIDTH == 8) ? {write_bus[7:0], write_bus[7:0]} : write_bus;
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assign pit_pre_scl = NO_PRESCALE ? 4'b0 : pit_pre;
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// generate wishbone write registers
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always_ff @(posedge bus_clk or negedge async_rst_b)
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if (!async_rst_b)
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begin
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pit_slave <= 1'b0;
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pit_pre <= 4'b0;
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pit_flg_clr <= 1'b0;
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pit_ien <= 1'b0;
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cnt_sync_o <= 1'b0;
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mod_value <= 0;
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end
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else if (sync_reset)
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begin
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pit_slave <= 1'b0;
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pit_pre <= 4'b0;
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pit_flg_clr <= 1'b0;
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pit_ien <= 1'b0;
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cnt_sync_o <= 1'b0;
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mod_value <= 0;
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end
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else
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case (write_regs) // synopsys parallel_case
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4'b0011 : // 16-bit write
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begin
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pit_slave <= write_data[15];
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pit_pre <= write_data[11:8];
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pit_flg_clr <= write_data[2];
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pit_ien <= write_data[1];
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cnt_sync_o <= write_data[0];
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end
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4'b0001 : // 8-bit low byte write
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begin
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pit_flg_clr <= write_data[2];
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pit_ien <= write_data[1];
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cnt_sync_o <= write_data[0];
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end
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4'b0010 : // 8-bit high byte write
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begin
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pit_slave <= write_data[7];
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pit_pre <= write_data[3:0];
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end
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4'b1100 : mod_value <= write_data;
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4'b0100 : mod_value[ 7:0] <= write_data[7:0];
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4'b1000 : mod_value[15:8] <= write_data[7:0];
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default:
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pit_flg_clr <= 1'b0;
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endcase
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// generate interrupt request signals
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always_ff @(posedge bus_clk or negedge async_rst_b)
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if (!async_rst_b)
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pit_irq_o <= 0;
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else if (sync_reset)
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pit_irq_o <= 0;
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else
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pit_irq_o <= cnt_flag_o && pit_ien; // interrupt signal is only generated
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// when IEN (interrupt enable bit is set)
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endmodule // pit_regs
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