OpenCores
URL https://opencores.org/ocsvn/pit/pit/trunk

Subversion Repositories pit

[/] [pit/] [trunk/] [sim/] [verilog/] [run/] [run_iverilog] - Blame information for rev 4

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 4 rehayes
#!/bin/csh
2
 
3
set pit      = ../../..
4
set bench    = $pit/bench
5
set wave_dir = $pit/sim/rtl_sim/pit_verilog/waves
6
 
7
iverilog                                \
8
                                        \
9
        -I $bench/verilog               \
10
        -I $pit/rtl/verilog             \
11
                        \
12
        -o pit_compiled \
13
        -D WAVES_V      \
14
                                        \
15
        $pit/rtl/verilog/pit_top.v      \
16
        $pit/rtl/verilog/pit_wb_bus.v   \
17
        $pit/rtl/verilog/pit_regs.v     \
18
        $pit/rtl/verilog/pit_prescale.v \
19
        $pit/rtl/verilog/pit_count.v    \
20
                                        \
21
        $bench/verilog/wb_master_model.v        \
22
        $bench/verilog/tst_bench_top.v
23
 
24
@ good_compile = $status
25
 
26
if ($good_compile == 0) then
27
  echo "Compile was Good"
28
  vvp pit_compiled -lxt2
29
else
30
  echo "Compile Failed"
31
endif
32
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.