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<b><font size=+2 face="Helvetica, Arial"
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color=#bf0000>Project Name: MIPS-lite core</font></b>
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<p>
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<font size=+1><b>Description</b></font>
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<P>
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MIPS-lite is a "clean room" VHDL implementation of a MIPS CPU.
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It supports a simplified MIPS III+ instruction set with a two-stage pipeline.
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Only User Mode instructions are supported.
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<p>
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<font size=+1><b>Block Diagram</b></font>
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<p>
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<center>
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<img src="cpu.gif">
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</center>
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<br>
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<font size=+1><b>Example Instruction</b></font>
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<p>
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As an example, an ADD instruction would take the following steps:
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<ol>
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<li>The "pc_next" entity would pass the program
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counter (PC) to the "mem_ctrl" entity. [First Stage of Pipeline]</li>
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<li>"Mem_ctrl" passes the opcode to the "control" entity.</li>
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<li>"Control" converts the 32-bit opcode to a 60-bit VLWI opcode
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and sends control signals to the other entities.</li>
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<li>Based on the rs_index and rt_index control signals, "reg_bank"
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sends the 32-bit reg_source and reg_target to "bus_mux".</li>
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<li>Based on the a_source and b_source control signals, "bus_mux"
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multiplexes reg_source onto a_bus and reg_target onto b_bus.</li>
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<li>Based on the alu_func control signals, "alu" adds the values
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from a_bus and b_bus and places the result on c_bus.</li>
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<li>Based on the c_source control signals, "bus_bux" multiplexes
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c_bus onto reg_dest.</li>
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<li>Based on the rd_index control signal, "reg_bank" saves
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reg_dest into the correct register.</li>
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</ol>
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<font size=+1><b>Features</b></font>
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<p>
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The CPU is implemented as a two-stage pipeline with step #1 in the
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first stage and steps #2-8 occurring the second stage.
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Each instruction takes one clock cycle, except memory accesses,
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which take two clock cycles, and multiplication and division, which
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can be accessed in 32 clock cycles.
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<br>
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<br>
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There are several control lines not shown in the diagram.
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A pause (wait-state) line will cause the pipeline to pause
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if the multiplication results are accessed before the
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multiplication is complete.
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<p>
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<font size=+1><b>Supporting Documentation</b></font>
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<p>
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The implementation is based on information found in:
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<ul>
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<li>"MIPS RISC Architecture" by Gerry Kane and Joe Heinrich and</li>
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<li>"The Designer's Guide to VHDL" by Peter J. Ashenden</li>
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</ul>
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<font size=+1><b>Tools</b></font>
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<p>
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The tools used include VHDL Synopsys, ModelTech, and the Microsoft
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MIPS C compiler.
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<p>
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<font size=+1><b>Registers</b></font>
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<p>
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All of the registers are clocked by the single master clock.
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The registers used in the design are grouped by entity and listed below:
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<pre width=80>
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mem_ctrl
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===========================================
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| Register Name | Type | Width |
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===========================================
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| next_opcode_reg_reg | Flip-flop | 32 |
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| opcode_reg_reg | Flip-flop | 32 |
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| setup_done_reg | Flip-flop | 1 |
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===========================================
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mult
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===========================================
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| Register Name | Type | Width |
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===========================================
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| answer_reg_reg | Flip-flop | 32 |
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| count_reg_reg | Flip-flop | 6 |
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| do_div_reg_reg | Flip-flop | 1 |
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| do_signed_reg_reg | Flip-flop | 1 |
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| reg_a_reg | Flip-flop | 32 |
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| reg_b_reg | Flip-flop | 64 |
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===========================================
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pc_next
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===========================================
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| Register Name | Type | Width |
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===========================================
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| pc_reg_reg | Flip-flop | 30 |
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===========================================
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reg_bank
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===========================================
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| Register Name | Type | Width |
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===========================================
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| reg01_reg | Flip-flop | 32 |
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| reg02_reg | Flip-flop | 32 |
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| reg03_reg | Flip-flop | 32 |
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| reg04_reg | Flip-flop | 32 |
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| reg05_reg | Flip-flop | 32 |
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| reg06_reg | Flip-flop | 32 |
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| reg07_reg | Flip-flop | 32 |
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| reg08_reg | Flip-flop | 32 |
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| reg09_reg | Flip-flop | 32 |
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| reg10_reg | Flip-flop | 32 |
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| reg11_reg | Flip-flop | 32 |
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| reg12_reg | Flip-flop | 32 |
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| reg13_reg | Flip-flop | 32 |
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| reg14_reg | Flip-flop | 32 |
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| reg15_reg | Flip-flop | 32 |
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| reg16_reg | Flip-flop | 32 |
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| reg17_reg | Flip-flop | 32 |
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| reg18_reg | Flip-flop | 32 |
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| reg19_reg | Flip-flop | 32 |
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| reg20_reg | Flip-flop | 32 |
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| reg21_reg | Flip-flop | 32 |
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| reg22_reg | Flip-flop | 32 |
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| reg23_reg | Flip-flop | 32 |
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| reg24_reg | Flip-flop | 32 |
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| reg25_reg | Flip-flop | 32 |
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| reg26_reg | Flip-flop | 32 |
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| reg27_reg | Flip-flop | 32 |
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| reg28_reg | Flip-flop | 32 |
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| reg29_reg | Flip-flop | 32 |
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| reg30_reg | Flip-flop | 32 |
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| reg31_reg | Flip-flop | 32 |
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| reg_epc_reg | Flip-flop | 32 |
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| reg_status_reg | Flip-flop | 1 |
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===========================================
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</pre>
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<font size=+1><b>Preliminary Synthesis</b></font>
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<p>
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The CPU core was synthesized for 0.13 um line widths with a predicted
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area less than 0.2 millimeters squared. The predicted maximum
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latency was less than 6 ns for a maximum clock speed of 150 MHz.
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<br>
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<br>
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A preliminary synthesis yields the following cells and die area.
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I think that optimization caused the mips_cpu entity
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to be smaller than the sum of its
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components.
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If one assumes that a standard cell is composed of three gates,
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then this is approximately a 20K gate design. [Is this correct??]
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It is interesting to note that the register bank requires over 60% of the area.
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<pre width=80>
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Block ports nets cells cell_area ~% delay(ns)
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------ ----- ---- ----- --------- --- ---------
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alu 101 919 850 7503 12 1.11
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bus_mux 283 672 486 4906 8 0.35
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control 93 296 263 2250 4 0.29
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mem_ctrl 271 455 318 3299 5 0.95
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mult 101 1111 1043 9342 15 0.72 ??
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pc_next 94 277 215 1756 3 0.15
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reg_bank 116 2650 2599 39477 62 1.02
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shifter 71 423 384 3026 5 1.51
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mips_cpu 201 555 45 63888 100 5.61
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total 1331 7358 6203
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</pre>
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<font size=+1><b>List of Files</b></font>
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<p>
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<ul>
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<table border="2" style="border-color:Black;border-collapse:collapse;">
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<tr>
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<td>FILE</td>
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<td>PURPOSE</td>
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</td><tr>
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</tr><tr>
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<td>makefile</td>
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<td>Makefile for the HP workstation for Synopsys</td>
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</tr><tr>
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<td>code.txt</td>
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<td>Input opcodes for the test bench -- test.exe "converted"</td>
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</tr><tr>
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<td>alu.vhd</td>
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<td>Arithmetic Logic Unit</td>
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</tr><tr>
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<td>bus_mux.vhd</td>
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<td>BUS Multiplex Unit</td>
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</tr><tr>
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<td>control.vhd</td>
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<td>Opcode Decoder</td>
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</tr><tr>
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<td>mem_ctrl.vhd</td>
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<td>Memory Controller</td>
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</tr><tr>
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<td>mips_cpu.vhd</td>
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<td>Top Level VHDL for MIPS CPU</td>
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</tr><tr>
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<td>mips_pack.vhd</td>
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<td>Constants and Functions Package</td>
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</tr><tr>
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<td>mult.vhd</td>
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<td>Multiplication and Division Unit</td>
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</tr><tr>
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<td>pc_next.vhd</td>
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<td>Program Counter Unit</td>
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</tr><tr>
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<td>ram.vhd</td>
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<td>RAM for the Test Bench</td>
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</tr><tr>
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<td>reg_bank.vhd</td>
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<td>Register Bank for 32, 32-bit Registers</td>
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</tr><tr>
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<td>shifter.vhd</td>
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<td>Shifter Unit</td>
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</tr><tr>
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<td>tbench.vhd</td>
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<td>Test Bench that uses mips_vpu.vhd and ram.vhd</td>
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</tr><tr>
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</tr><tr>
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<td>makefile</td>
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<td>Makefile for the PC for creating "code.txt"</td>
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</tr><tr>
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<td>convert.c</td>
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<td>Converts test.exe to code.txt</td>
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</tr><tr>
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<td>mips.c</td>
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<td>Simulates a MIPS CPU in software</td>
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</tr><tr>
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<td>test.c</td>
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<td>Test program (opcodes) for the MIPS CPU</td>
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</tr><tr>
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<td>output.txt</td>
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<td>Output from the test bench</td>
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</tr><tr>
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<td>index.shtml</td>
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<td>This help file</td>
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</tr><tr>
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<td>cpu.gif</td>
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<td>Block Diagram</td>
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</tr>
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</table>
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</ul>
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<p>
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<font size=+1><b>ZIP File</b></font>
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<p>
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CVS is the only way to download the latest files. However
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for a quick look at an old version you can download
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<a href="mipslite.zip">MIPSlite.zip</a>.
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<p>
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<font size=+1><b>Convert</b></font>
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<p>
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The program "convert" changes the file "test.exe" into the HEX file "code.txt".
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The opcodes in "test.exe" are changed to Big Endian.
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All absolute jumps are changed to relative jumps.
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The first opcode is also changed to set up the stack pointer.
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<p>
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<font size=+1><b>Big/Little Endian</b></font>
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<p>
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The MIPS CPU operates in Big Endian mode by default. To operate in
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Little Endian mode, change "little_endian" from "00" to "11" in
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the file mem_ctrl.vhd.
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<p>
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<font size=+1><b>Legal Notice</b></font>
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<p>
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<font color="#FF0000">
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MIPS is a registered trademark of MIPS Technologies, Inc.
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If you use this core you are responsible for all legal issues.
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This "clean room" implementation of a MIPS CPU does not negate
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MIPS Technologies, Inc. of their trademark, copyrights, or patents....
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<p>
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Free for commercial and non-commercial use as long as the author and
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warning notices are maintained.
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<br>
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<br>
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This software is provided by Steve Rhoads "as is" and
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any express or implied warranties, including, but not limited to, the
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implied warranties of merchantability and fitness for a particular purpose
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are disclaimed. In no event shall the author or contributors be liable
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for any direct, indirect, incidental, special, exemplary, or consequential
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damages (including, but not limited to, procurement of substitute goods
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or services; loss of use, data, or profits; or business interruption)
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however caused and on any theory of liability, whether in contract, strict
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liability, or tort (including negligence or otherwise) arising in any way
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out of the use of this software, even if advised of the possibility of
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such damage.
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</font>
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<p>
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<p><b><font size="+1">Bus Interface</font></b></p>
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<p>
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<pre width=80>
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port(clk : in std_logic;
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reset_in : in std_logic;
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intr_in : in std_logic; --interrupt line
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--memory access buses
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mem_address : out std_logic_vector(31 downto 0);
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mem_data_w : out std_logic_vector(31 downto 0); --avoided tri-state
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mem_data_r : in std_logic_vector(31 downto 0);
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mem_sel : out std_logic_vector(3 downto 0); --byte lines
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mem_write : out std_logic;
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mem_pause : in std_logic
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);
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</pre>
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<p>
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<font size=+1><b>Current Status</b></font>
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<ul>
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<li>The test bench needs to be strengthened.</li>
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<li>Need feedback on the design.</li>
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<li>Need feedback on the tools.</li>
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<li>Need to add simulation of a cache.</li>
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</ul>
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<p>
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<font size=+1><b>Maintainer</b></font>
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<ul>Steve Rhoads,
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<a href="mailto:rhoads@opencores.org_NOSPAM">rhoads@opencores.org_NOSPAM</a></ul>
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<p>
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<ul>*** I am not an experienced VHDL designer ***
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Please let me know of any incorrect statements in this document.</ul>
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<p>
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<font size=+1><b>Mailing-list</b></font>
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<p>
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<ul><a href=mailto:cores@opencores.org_NOSPAM>cores@opencores.org_NOSPAM</A></ul>
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