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rhoads |
---------------------------------------------------------------------
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-- TITLE: MIPS CPU core
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-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
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-- DATE CREATED: 2/15/01
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-- FILENAME: mips_cpu.vhd
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-- PROJECT: MIPS CPU core
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-- COPYRIGHT: Software placed into the public domain by the author.
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-- Software 'as is' without warranty. Author liable for nothing.
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-- DESCRIPTION:
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-- Top level VHDL document that ties the eight other entities together.
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-- Implements a MIPS CPU. Based on information found in:
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-- "MIPS RISC Architecture" by Gerry Kane and Joe Heinrich
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-- and "The Designer's Guide to VHDL" by Peter J. Ashenden
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-- An add instruction would take the following steps (see cpu.gif):
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-- 1. The "pc_next" entity would have previously passed the program
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-- counter (PC) to the "mem_ctrl" entity.
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-- 2. "Mem_ctrl" passes the opcode to the "control" entity.
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-- 3. "Control" converts the 32-bit opcode to a 60-bit VLWI opcode
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-- and sends control signals to the other entities.
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-- 4. Based on the rs_index and rt_index control signals, "reg_bank"
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-- sends the 32-bit reg_source and reg_target to "bus_mux".
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-- 5. Based on the a_source and b_source control signals, "bus_mux"
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-- multiplexes reg_source onto a_bus and reg_target onto b_bus.
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-- 6. Based on the alu_func control signals, "alu" adds the values
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-- from a_bus and b_bus and places the result on c_bus.
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-- 7. Based on the c_source control signals, "bus_bux" multiplexes
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-- c_bus onto reg_dest.
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-- 8. Based on the rd_index control signal, "reg_bank" saves
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-- reg_dest into the correct register.
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-- The CPU is implemented as a two stage pipeline with step #1 in the
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-- first stage and steps #2-8 occuring the second stage.
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--
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-- The CPU core was synthesized for 0.13 um line widths with an area
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-- of 0.2 millimeters squared. The maximum latency was less than 6 ns
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-- for a maximum clock speed of 150 MHz.
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---------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.mips_pack.all;
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entity mips_cpu is
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port(clk : in std_logic;
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reset_in : in std_logic;
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intr_in : in std_logic;
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mem_address : out std_logic_vector(31 downto 0);
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mem_data_w : out std_logic_vector(31 downto 0);
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mem_data_r : in std_logic_vector(31 downto 0);
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mem_sel : out std_logic_vector(3 downto 0);
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mem_write : out std_logic;
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mem_pause : in std_logic;
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t_pc : out std_logic_vector(31 downto 0);
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t_opcode : out std_logic_vector(31 downto 0);
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t_r_dest : out std_logic_vector(31 downto 0)
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);
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end; --entity mips_cpu
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architecture logic of mips_cpu is
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component pc_next
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port(clk : in std_logic;
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reset_in : in std_logic;
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pc_new : in std_logic_vector(31 downto 2);
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take_branch : in std_logic;
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pause_in : in std_logic;
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opcode25_0 : in std_logic_vector(25 downto 0);
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pc_source : in pc_source_type;
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pc_out : out std_logic_vector(31 downto 0));
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end component;
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component mem_ctrl
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port(clk : in std_logic;
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reset_in : in std_logic;
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pause_in : in std_logic;
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nullify_op : in std_logic;
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address_pc : in std_logic_vector(31 downto 0);
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opcode_out : out std_logic_vector(31 downto 0);
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address_data : in std_logic_vector(31 downto 0);
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mem_source : in mem_source_type;
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data_write : in std_logic_vector(31 downto 0);
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data_read : out std_logic_vector(31 downto 0);
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pause_out : out std_logic;
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mem_address : out std_logic_vector(31 downto 0);
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mem_data_w : out std_logic_vector(31 downto 0);
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mem_data_r : in std_logic_vector(31 downto 0);
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mem_byte_sel : out std_logic_vector(3 downto 0);
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mem_write : out std_logic;
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mem_pause : in std_logic);
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end component;
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component control
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port(opcode : in std_logic_vector(31 downto 0);
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intr_signal : in std_logic;
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rs_index : out std_logic_vector(5 downto 0);
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rt_index : out std_logic_vector(5 downto 0);
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rd_index : out std_logic_vector(5 downto 0);
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imm_out : out std_logic_vector(15 downto 0);
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alu_func : out alu_function_type;
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shift_func : out shift_function_type;
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mult_func : out mult_function_type;
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branch_func : out branch_function_type;
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a_source_out : out a_source_type;
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b_source_out : out b_source_type;
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c_source_out : out c_source_type;
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pc_source_out: out pc_source_type;
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mem_source_out:out mem_source_type);
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end component;
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component reg_bank
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port(clk : in std_logic;
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rs_index : in std_logic_vector(5 downto 0);
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rt_index : in std_logic_vector(5 downto 0);
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rd_index : in std_logic_vector(5 downto 0);
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reg_source_out : out std_logic_vector(31 downto 0);
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reg_target_out : out std_logic_vector(31 downto 0);
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reg_dest_new : in std_logic_vector(31 downto 0);
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intr_enable : out std_logic);
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end component;
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component bus_mux
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port(imm_in : in std_logic_vector(15 downto 0);
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reg_source : in std_logic_vector(31 downto 0);
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a_mux : in a_source_type;
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a_out : out std_logic_vector(31 downto 0);
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reg_target : in std_logic_vector(31 downto 0);
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b_mux : in b_source_type;
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b_out : out std_logic_vector(31 downto 0);
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c_bus : in std_logic_vector(31 downto 0);
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c_memory : in std_logic_vector(31 downto 0);
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c_pc : in std_logic_vector(31 downto 0);
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c_mux : in c_source_type;
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reg_dest_out : out std_logic_vector(31 downto 0);
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branch_func : in branch_function_type;
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take_branch : out std_logic);
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end component;
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component alu
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port(a_in : in std_logic_vector(31 downto 0);
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b_in : in std_logic_vector(31 downto 0);
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alu_function : in alu_function_type;
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c_alu : out std_logic_vector(31 downto 0));
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end component;
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component shifter
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port(value : in std_logic_vector(31 downto 0);
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shift_amount : in std_logic_vector(4 downto 0);
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shift_func : in shift_function_type;
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c_shift : out std_logic_vector(31 downto 0));
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end component;
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component mult
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port(clk : in std_logic;
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a, b : in std_logic_vector(31 downto 0);
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mult_func : in mult_function_type;
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c_mult : out std_logic_vector(31 downto 0);
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pause_out : out std_logic);
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end component;
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signal opcode : std_logic_vector(31 downto 0);
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signal rs_index, rt_index, rd_index : std_logic_vector(5 downto 0);
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signal reg_source, reg_target, reg_dest : std_logic_vector(31 downto 0);
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signal a_bus, b_bus, c_bus : std_logic_vector(31 downto 0);
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signal c_alu, c_shift, c_mult, c_memory
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: std_logic_vector(31 downto 0);
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signal imm : std_logic_vector(15 downto 0);
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signal pc : std_logic_vector(31 downto 0);
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signal alu_function : alu_function_type;
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signal shift_function : shift_function_type;
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signal mult_function : mult_function_type;
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signal branch_function: branch_function_type;
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signal take_branch : std_logic;
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signal a_source : a_source_type;
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signal b_source : b_source_type;
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signal c_source : c_source_type;
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signal pc_source : pc_source_type;
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signal mem_source : mem_source_type;
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signal pause_mult : std_logic;
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signal pause_memory : std_logic;
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signal pause : std_logic;
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signal nullify_op : std_logic;
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signal intr_enable : std_logic;
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signal intr_signal : std_logic;
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-- signal mem_byte_sel : std_logic_vector(3 downto 0);
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-- signal mem_write : std_logic;
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begin --architecture
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pause <= pause_mult or pause_memory;
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--nulify_op = pc_source==from_lbranch && take_branch=='0'
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nullify_op <= pc_source(1) and pc_source(0) and not take_branch;
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c_bus <= c_alu or c_shift or c_mult;
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intr_signal <= (intr_in and intr_enable) and
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(not pc_source(0) and not pc_source(1)); --from_inc4
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u1: pc_next PORT MAP (
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clk => clk,
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reset_in => reset_in,
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take_branch => take_branch,
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pause_in => pause,
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pc_new => c_alu(31 downto 2),
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opcode25_0 => opcode(25 downto 0),
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pc_source => pc_source,
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pc_out => pc);
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u2: mem_ctrl PORT MAP (
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clk => clk,
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reset_in => reset_in,
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pause_in => pause,
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nullify_op => nullify_op,
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address_pc => pc,
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opcode_out => opcode,
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address_data => c_alu,
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mem_source => mem_source,
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data_write => reg_target,
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data_read => c_memory,
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pause_out => pause_memory,
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mem_address => mem_address,
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mem_data_w => mem_data_w,
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mem_data_r => mem_data_r,
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mem_byte_sel => mem_sel,
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mem_write => mem_write,
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mem_pause => mem_pause);
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u3: control PORT MAP (
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opcode => opcode,
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intr_signal => intr_signal,
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rs_index => rs_index,
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rt_index => rt_index,
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rd_index => rd_index,
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imm_out => imm,
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alu_func => alu_function,
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shift_func => shift_function,
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mult_func => mult_function,
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branch_func => branch_function,
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a_source_out => a_source,
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b_source_out => b_source,
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c_source_out => c_source,
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pc_source_out=> pc_source,
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mem_source_out=> mem_source);
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u4: reg_bank port map (
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clk => clk,
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rs_index => rs_index,
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rt_index => rt_index,
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rd_index => rd_index,
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reg_source_out => reg_source,
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reg_target_out => reg_target,
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reg_dest_new => reg_dest,
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intr_enable => intr_enable);
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u5: bus_mux port map (
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imm_in => imm,
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reg_source => reg_source,
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a_mux => a_source,
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a_out => a_bus,
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reg_target => reg_target,
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b_mux => b_source,
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b_out => b_bus,
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c_bus => c_bus,
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c_memory => c_memory,
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c_pc => pc,
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c_mux => c_source,
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reg_dest_out => reg_dest,
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branch_func => branch_function,
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take_branch => take_branch);
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u6: alu port map (
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a_in => a_bus,
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b_in => b_bus,
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alu_function => alu_function,
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c_alu => c_alu);
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u7: shifter port map (
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value => b_bus,
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shift_amount => a_bus(4 downto 0),
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shift_func => shift_function,
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c_shift => c_shift);
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u8: mult port map (
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clk => clk,
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a => a_bus,
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b => b_bus,
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mult_func => mult_function,
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c_mult => c_mult,
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pause_out => pause_mult);
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t_pc <= pc;
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t_opcode <= opcode;
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t_r_dest <= reg_dest;
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end; --architecture logic
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