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1 2 rhoads 
---------------------------------------------------------------------
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-- TITLE: Register Bank
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-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
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-- DATE CREATED: 2/2/01
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-- FILENAME: reg_bank.vhd
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-- PROJECT: MIPS CPU core
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-- COPYRIGHT: Software placed into the public domain by the author.
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--    Software 'as is' without warranty.  Author liable for nothing.
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-- DESCRIPTION:
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--    Implements a register bank with 32 registers that are 32-bits wide.
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--    There are two read-ports and one write port.
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---------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.mips_pack.all;
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entity reg_bank is
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   port(clk            : in  std_logic;
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        rs_index       : in  std_logic_vector(5 downto 0);
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        rt_index       : in  std_logic_vector(5 downto 0);
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        rd_index       : in  std_logic_vector(5 downto 0);
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        reg_source_out : out std_logic_vector(31 downto 0);
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        reg_target_out : out std_logic_vector(31 downto 0);
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        reg_dest_new   : in  std_logic_vector(31 downto 0);
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        intr_enable    : out std_logic);
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end; --entity reg_bank
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architecture logic of reg_bank is
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   signal reg31, reg01, reg02, reg03 : std_logic_vector(31 downto 0);
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   --For Altera simulations, comment out reg04 through reg30
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   signal reg04, reg05, reg06, reg07 : std_logic_vector(31 downto 0);
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   signal reg08, reg09, reg10, reg11 : std_logic_vector(31 downto 0);
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   signal reg12, reg13, reg14, reg15 : std_logic_vector(31 downto 0);
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   signal reg16, reg17, reg18, reg19 : std_logic_vector(31 downto 0);
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   signal reg20, reg21, reg22, reg23 : std_logic_vector(31 downto 0);
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   signal reg24, reg25, reg26, reg27 : std_logic_vector(31 downto 0);
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   signal reg28, reg29, reg30        : std_logic_vector(31 downto 0);
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   signal reg_epc                    : std_logic_vector(31 downto 0);
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   signal reg_status                 : std_logic;
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begin
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reg_proc: process(clk, rs_index, rt_index, rd_index, reg_dest_new,
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   reg31, reg01, reg02, reg03, reg04, reg05, reg06, reg07,
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   reg08, reg09, reg10, reg11, reg12, reg13, reg14, reg15,
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   reg16, reg17, reg18, reg19, reg20, reg21, reg22, reg23,
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   reg24, reg25, reg26, reg27, reg28, reg29, reg30,
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   reg_epc, reg_status)
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begin
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   case rs_index is
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   when "000000" => reg_source_out <= ZERO;
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   when "000001" => reg_source_out <= reg01;
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   when "000010" => reg_source_out <= reg02;
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   when "000011" => reg_source_out <= reg03;
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   when "000100" => reg_source_out <= reg04;
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   when "000101" => reg_source_out <= reg05;
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   when "000110" => reg_source_out <= reg06;
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   when "000111" => reg_source_out <= reg07;
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   when "001000" => reg_source_out <= reg08;
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   when "001001" => reg_source_out <= reg09;
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   when "001010" => reg_source_out <= reg10;
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   when "001011" => reg_source_out <= reg11;
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   when "001100" => reg_source_out <= reg12;
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   when "001101" => reg_source_out <= reg13;
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   when "001110" => reg_source_out <= reg14;
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   when "001111" => reg_source_out <= reg15;
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   when "010000" => reg_source_out <= reg16;
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   when "010001" => reg_source_out <= reg17;
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   when "010010" => reg_source_out <= reg18;
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   when "010011" => reg_source_out <= reg19;
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   when "010100" => reg_source_out <= reg20;
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   when "010101" => reg_source_out <= reg21;
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   when "010110" => reg_source_out <= reg22;
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   when "010111" => reg_source_out <= reg23;
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   when "011000" => reg_source_out <= reg24;
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   when "011001" => reg_source_out <= reg25;
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   when "011010" => reg_source_out <= reg26;
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   when "011011" => reg_source_out <= reg27;
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   when "011100" => reg_source_out <= reg28;
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   when "011101" => reg_source_out <= reg29;
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   when "011110" => reg_source_out <= reg30;
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   when "011111" => reg_source_out <= reg31;
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   when "101100" => reg_source_out <= ZERO(31 downto 1) & reg_status;
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   when "101110" => reg_source_out <= reg_epc;     --CP0 14
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   when "111111" => reg_source_out <= '1' & ZERO(30 downto 0); --intr vector
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   when others =>   reg_source_out <= ZERO;
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   end case;
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   case rt_index is
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   when "000000" => reg_target_out <= ZERO;
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   when "000001" => reg_target_out <= reg01;
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   when "000010" => reg_target_out <= reg02;
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   when "000011" => reg_target_out <= reg03;
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   when "000100" => reg_target_out <= reg04;
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   when "000101" => reg_target_out <= reg05;
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   when "000110" => reg_target_out <= reg06;
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   when "000111" => reg_target_out <= reg07;
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   when "001000" => reg_target_out <= reg08;
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   when "001001" => reg_target_out <= reg09;
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   when "001010" => reg_target_out <= reg10;
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   when "001011" => reg_target_out <= reg11;
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   when "001100" => reg_target_out <= reg12;
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   when "001101" => reg_target_out <= reg13;
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   when "001110" => reg_target_out <= reg14;
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   when "001111" => reg_target_out <= reg15;
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   when "010000" => reg_target_out <= reg16;
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   when "010001" => reg_target_out <= reg17;
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   when "010010" => reg_target_out <= reg18;
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   when "010011" => reg_target_out <= reg19;
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   when "010100" => reg_target_out <= reg20;
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   when "010101" => reg_target_out <= reg21;
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   when "010110" => reg_target_out <= reg22;
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   when "010111" => reg_target_out <= reg23;
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   when "011000" => reg_target_out <= reg24;
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   when "011001" => reg_target_out <= reg25;
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   when "011010" => reg_target_out <= reg26;
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   when "011011" => reg_target_out <= reg27;
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   when "011100" => reg_target_out <= reg28;
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   when "011101" => reg_target_out <= reg29;
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   when "011110" => reg_target_out <= reg30;
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   when "011111" => reg_target_out <= reg31;
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   when others =>   reg_target_out <= ZERO;
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   end case;
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   if rising_edge(clk) then
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--      assert reg_dest_new'last_event >= 10 ns
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--         report "Reg_dest timing error";
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      case rd_index is
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      when "000001" => reg01 <= reg_dest_new;
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      when "000010" => reg02 <= reg_dest_new;
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      when "000011" => reg03 <= reg_dest_new;
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      when "000100" => reg04 <= reg_dest_new;
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      when "000101" => reg05 <= reg_dest_new;
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      when "000110" => reg06 <= reg_dest_new;
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      when "000111" => reg07 <= reg_dest_new;
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      when "001000" => reg08 <= reg_dest_new;
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      when "001001" => reg09 <= reg_dest_new;
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      when "001010" => reg10 <= reg_dest_new;
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      when "001011" => reg11 <= reg_dest_new;
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      when "001100" => reg12 <= reg_dest_new;
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      when "001101" => reg13 <= reg_dest_new;
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      when "001110" => reg14 <= reg_dest_new;
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      when "001111" => reg15 <= reg_dest_new;
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      when "010000" => reg16 <= reg_dest_new;
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      when "010001" => reg17 <= reg_dest_new;
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      when "010010" => reg18 <= reg_dest_new;
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      when "010011" => reg19 <= reg_dest_new;
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      when "010100" => reg20 <= reg_dest_new;
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      when "010101" => reg21 <= reg_dest_new;
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      when "010110" => reg22 <= reg_dest_new;
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      when "010111" => reg23 <= reg_dest_new;
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      when "011000" => reg24 <= reg_dest_new;
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      when "011001" => reg25 <= reg_dest_new;
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      when "011010" => reg26 <= reg_dest_new;
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      when "011011" => reg27 <= reg_dest_new;
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      when "011100" => reg28 <= reg_dest_new;
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      when "011101" => reg29 <= reg_dest_new;
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      when "011110" => reg30 <= reg_dest_new;
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      when "011111" => reg31 <= reg_dest_new;
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      when "101100" => reg_status <= reg_dest_new(0);
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      when "101110" => reg_epc <= reg_dest_new;  --CP0 14
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                       reg_status <= '0';        --disable interrupts
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      when others =>
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      end case;
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   end if;
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   intr_enable <= reg_status;
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end process;
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end; --architecture logic
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