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rhoads |
---------------------------------------------------------------------
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-- TITLE: MIPS Misc. Package
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-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
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-- DATE CREATED: 2/15/01
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-- FILENAME: mips_pack.vhd
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-- PROJECT: MIPS CPU core
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-- COPYRIGHT: Software placed into the public domain by the author.
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-- Software 'as is' without warranty. Author liable for nothing.
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-- DESCRIPTION:
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-- Data types, constants, and add functions needed for the MIPS CPU.
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---------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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package mips_pack is
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constant ZERO : std_logic_vector(31 downto 0) :=
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"00000000000000000000000000000000";
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constant ONES : std_logic_vector(31 downto 0) :=
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"11111111111111111111111111111111";
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-- type alu_function_type is (alu_nothing, alu_add, alu_subtract,
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-- alu_less_than, alu_less_than_signed, alu_equal, alu_not_equal,
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-- alu_ltz, alu_lez, alu_eqz, alu_nez, alu_gez, alu_gtz,
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-- alu_or, alu_and, alu_xor, alu_nor);
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subtype alu_function_type is std_logic_vector(4 downto 0);
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constant alu_nothing : alu_function_type := "00000";
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constant alu_add : alu_function_type := "00010";
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constant alu_subtract : alu_function_type := "00011";
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constant alu_less_than : alu_function_type := "00100";
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constant alu_less_than_signed : alu_function_type := "00101";
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constant alu_equal : alu_function_type := "00110";
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constant alu_not_equal : alu_function_type := "00111";
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constant alu_ltz : alu_function_type := "01000";
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constant alu_lez : alu_function_type := "01001";
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constant alu_eqz : alu_function_type := "01010";
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constant alu_nez : alu_function_type := "01011";
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constant alu_gez : alu_function_type := "01100";
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constant alu_gtz : alu_function_type := "01101";
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constant alu_or : alu_function_type := "01110";
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constant alu_and : alu_function_type := "01111";
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constant alu_xor : alu_function_type := "10001";
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constant alu_nor : alu_function_type := "10010";
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-- type shift_function_type is (
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-- shift_nothing, shift_left_unsigned,
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-- shift_right_signed, do_right_unsigned);
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subtype shift_function_type is std_logic_vector(1 downto 0);
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constant shift_nothing : shift_function_type := "00";
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constant shift_left_unsigned : shift_function_type := "01";
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constant shift_right_signed : shift_function_type := "11";
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constant shift_right_unsigned : shift_function_type := "10";
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-- type mult_function_type is (
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-- mult_nothing, mult_read_lo, mult_read_hi, mult_write_lo,
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-- mult_write_hi, mult_mult, mult_divide, mult_signed_divide);
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subtype mult_function_type is std_logic_vector(2 downto 0);
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constant mult_nothing : mult_function_type := "000";
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constant mult_read_lo : mult_function_type := "001";
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constant mult_read_hi : mult_function_type := "010";
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constant mult_write_lo : mult_function_type := "011";
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constant mult_write_hi : mult_function_type := "100";
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constant mult_mult : mult_function_type := "101";
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constant mult_divide : mult_function_type := "110";
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constant mult_signed_divide : mult_function_type := "111";
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-- type a_source_type is (from_reg_source, from_imm10_6);
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subtype a_source_type is std_logic_vector(1 downto 0);
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constant a_from_reg_source : a_source_type := "00";
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constant a_from_imm10_6 : a_source_type := "01";
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constant a_from_pc : a_source_type := "10";
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-- type b_source_type is (from_reg_target, from_imm, from_signed_imm);
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subtype b_source_type is std_logic_vector(1 downto 0);
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constant b_from_reg_target : b_source_type := "00";
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constant b_from_imm : b_source_type := "01";
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constant b_from_signed_imm : b_source_type := "10";
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constant b_from_immX4 : b_source_type := "11";
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-- type c_source_type is (from_null, from_alu, from_shift,
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-- from_mult, from_memory, from_pc, from_imm_shift16,
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-- from_reg_source_nez, from_reg_source_eqz);
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subtype c_source_type is std_logic_vector(2 downto 0);
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constant c_from_alu : c_source_type := "000";
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constant c_from_shift : c_source_type := "001";
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constant c_from_mult : c_source_type := "010";
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constant c_from_memory : c_source_type := "011";
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constant c_from_pc : c_source_type := "100";
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constant c_from_imm_shift16: c_source_type := "101";
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constant c_from_reg_sourcen: c_source_type := "110";
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constant c_from_null : c_source_type := "111";
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-- type pc_source_type is (from_inc4, from_inc8, from_reg_source,
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-- from_opcode25_0, from_branch, from_lbranch);
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subtype pc_source_type is std_logic_vector(1 downto 0);
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constant from_inc4 : pc_source_type := "00";
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constant from_opcode25_0 : pc_source_type := "01";
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constant from_branch : pc_source_type := "10";
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constant from_lbranch : pc_source_type := "11";
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subtype branch_function_type is std_logic_vector(2 downto 0);
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constant branch_ltz : branch_function_type := "000";
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constant branch_lez : branch_function_type := "001";
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constant branch_eq : branch_function_type := "010";
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constant branch_ne : branch_function_type := "011";
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constant branch_gez : branch_function_type := "100";
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constant branch_gtz : branch_function_type := "101";
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constant branch_yes : branch_function_type := "110";
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-- mode(32=1,16=2,8=3), signed, write
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subtype mem_source_type is std_logic_vector(3 downto 0);
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constant mem_none : mem_source_type := "0000";
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constant mem_read32 : mem_source_type := "0100";
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constant mem_write32 : mem_source_type := "0101";
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constant mem_read16 : mem_source_type := "1000";
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constant mem_read16s : mem_source_type := "1010";
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constant mem_write16 : mem_source_type := "1001";
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constant mem_read8 : mem_source_type := "1100";
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constant mem_read8s : mem_source_type := "1110";
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constant mem_write8 : mem_source_type := "1101";
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function bv_to_integer(bv: in std_logic_vector) return integer;
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function bv_adder(a : in std_logic_vector(32 downto 0);
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b : in std_logic_vector(32 downto 0);
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do_sub: in std_logic) return std_logic_vector;
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function bv_adder_lookahead(
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a : in std_logic_vector(32 downto 0);
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b : in std_logic_vector(32 downto 0);
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do_sub: in std_logic) return std_logic_vector;
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function bv_negate(a : in std_logic_vector) return std_logic_vector;
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function bv_increment(a : in std_logic_vector(31 downto 2)
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) return std_logic_vector;
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function bv_inc6(a : in std_logic_vector
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) return std_logic_vector;
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end; --package mips_pack
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package body mips_pack is
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function add_1(a:integer) return integer is
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begin
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return a+1;
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end; --function
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function bv_to_integer(bv: in std_logic_vector) return integer is
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variable result : integer;
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variable b : integer;
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begin
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result := 0;
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b := 0;
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for index in bv'range loop
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if bv(index) = '1' then
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b := 1;
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else
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b := 0;
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end if;
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result := result * 2 + b;
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end loop;
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return result;
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end; --function bv_to_integer
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function bv_adder(a : in std_logic_vector(32 downto 0);
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b : in std_logic_vector(32 downto 0);
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do_sub: in std_logic) return std_logic_vector is
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variable carry_in : std_logic;
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variable bb : std_logic_vector(32 downto 0);
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variable result : std_logic_vector(32 downto 0);
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begin
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result := "000000000000000000000000000000000";
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if do_sub = '0' then
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bb := b;
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carry_in := '0';
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else
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bb := not b;
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carry_in := '1';
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end if;
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for index in 0 to 32 loop
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result(index) := a(index) xor bb(index) xor carry_in;
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carry_in := (carry_in and (a(index) or bb(index))) or
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(a(index) and bb(index));
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end loop;
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return result;
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end; --function
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function bv_adder_lookahead(
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a : in std_logic_vector(32 downto 0);
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b : in std_logic_vector(32 downto 0);
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do_sub: in std_logic) return std_logic_vector is
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variable carry : std_logic_vector(32 downto 0);
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variable p, g : std_logic_vector(32 downto 0);
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variable bb : std_logic_vector(32 downto 0);
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variable result : std_logic_vector(32 downto 0);
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variable i : natural;
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begin
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carry := "000000000000000000000000000000000";
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if do_sub = '0' then
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bb := b;
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carry(0) := '0';
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else
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bb := not b;
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carry(0) := '1';
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end if;
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p := a or bb; --propogate
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g := a and bb; --generate
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for index in 0 to 7 loop
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i := index*4;
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carry(i+1) := g(i) or
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(p(i) and carry(i));
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i := index*4+1;
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carry(i+1) := g(i) or
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(p(i) and g(i-1)) or
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((p(i) and p(i-1)) and carry(i-1));
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i := index*4+2;
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carry(i+1) := g(i) or
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(p(i) and g(i-1)) or
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(p(i) and p(i-1) and g(i-2)) or
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((p(i) and p(i-1) and p(i-2)) and carry(i-2));
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i := index*4+3;
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carry(i+1) := g(i) or
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(p(i) and g(i-1)) or
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(p(i) and p(i-1) and g(i-2)) or
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(p(i) and p(i-1) and p(i-2) and g(i-3)) or
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(((p(i) and p(i-1)) and (p(i-2) and p(i-3)))
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and carry(i-3));
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end loop;
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result := (a xor bb) xor carry;
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return result;
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end; --function
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function bv_negate(a : in std_logic_vector) return std_logic_vector is
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variable carry_in : std_logic;
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variable not_a : std_logic_vector(31 downto 0);
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variable result : std_logic_vector(31 downto 0);
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begin
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result := ZERO;
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not_a := not a;
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carry_in := '1';
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for index in a'reverse_range loop
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result(index) := not_a(index) xor carry_in;
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carry_in := carry_in and not_a(index);
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end loop;
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return result;
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end; --function
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function bv_increment(a : in std_logic_vector(31 downto 2)
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) return std_logic_vector is
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variable carry_in : std_logic;
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variable result : std_logic_vector(31 downto 2);
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begin
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result := "000000000000000000000000000000";
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carry_in := '1';
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for index in 2 to 31 loop
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result(index) := a(index) xor carry_in;
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carry_in := a(index) and carry_in;
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end loop;
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return result;
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end; --function
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function bv_inc6(a : in std_logic_vector
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) return std_logic_vector is
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variable carry_in : std_logic;
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variable result : std_logic_vector(5 downto 0);
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begin
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result := "000000";
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carry_in := '1';
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for index in 0 to 5 loop
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result(index) := a(index) xor carry_in;
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carry_in := a(index) and carry_in;
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end loop;
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return result;
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end; --function
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end; --package body
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