1 |
2 |
rhoads |
---------------------------------------------------------------------
|
2 |
|
|
-- TITLE: Register Bank
|
3 |
|
|
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
|
4 |
|
|
-- DATE CREATED: 2/2/01
|
5 |
|
|
-- FILENAME: reg_bank.vhd
|
6 |
|
|
-- PROJECT: MIPS CPU core
|
7 |
|
|
-- COPYRIGHT: Software placed into the public domain by the author.
|
8 |
|
|
-- Software 'as is' without warranty. Author liable for nothing.
|
9 |
|
|
-- DESCRIPTION:
|
10 |
|
|
-- Implements a register bank with 32 registers that are 32-bits wide.
|
11 |
|
|
-- There are two read-ports and one write port.
|
12 |
|
|
---------------------------------------------------------------------
|
13 |
|
|
library ieee;
|
14 |
|
|
use ieee.std_logic_1164.all;
|
15 |
|
|
use work.mips_pack.all;
|
16 |
|
|
|
17 |
|
|
entity reg_bank is
|
18 |
|
|
port(clk : in std_logic;
|
19 |
|
|
rs_index : in std_logic_vector(5 downto 0);
|
20 |
|
|
rt_index : in std_logic_vector(5 downto 0);
|
21 |
|
|
rd_index : in std_logic_vector(5 downto 0);
|
22 |
|
|
reg_source_out : out std_logic_vector(31 downto 0);
|
23 |
|
|
reg_target_out : out std_logic_vector(31 downto 0);
|
24 |
|
|
reg_dest_new : in std_logic_vector(31 downto 0);
|
25 |
|
|
intr_enable : out std_logic);
|
26 |
|
|
end; --entity reg_bank
|
27 |
|
|
|
28 |
|
|
architecture logic of reg_bank is
|
29 |
|
|
signal reg31, reg01, reg02, reg03 : std_logic_vector(31 downto 0);
|
30 |
|
|
--For Altera simulations, comment out reg04 through reg30
|
31 |
|
|
signal reg04, reg05, reg06, reg07 : std_logic_vector(31 downto 0);
|
32 |
|
|
signal reg08, reg09, reg10, reg11 : std_logic_vector(31 downto 0);
|
33 |
|
|
signal reg12, reg13, reg14, reg15 : std_logic_vector(31 downto 0);
|
34 |
|
|
signal reg16, reg17, reg18, reg19 : std_logic_vector(31 downto 0);
|
35 |
|
|
signal reg20, reg21, reg22, reg23 : std_logic_vector(31 downto 0);
|
36 |
|
|
signal reg24, reg25, reg26, reg27 : std_logic_vector(31 downto 0);
|
37 |
|
|
signal reg28, reg29, reg30 : std_logic_vector(31 downto 0);
|
38 |
|
|
signal reg_epc : std_logic_vector(31 downto 0);
|
39 |
|
|
signal reg_status : std_logic;
|
40 |
|
|
begin
|
41 |
|
|
|
42 |
|
|
reg_proc: process(clk, rs_index, rt_index, rd_index, reg_dest_new,
|
43 |
|
|
reg31, reg01, reg02, reg03, reg04, reg05, reg06, reg07,
|
44 |
|
|
reg08, reg09, reg10, reg11, reg12, reg13, reg14, reg15,
|
45 |
|
|
reg16, reg17, reg18, reg19, reg20, reg21, reg22, reg23,
|
46 |
|
|
reg24, reg25, reg26, reg27, reg28, reg29, reg30,
|
47 |
|
|
reg_epc, reg_status)
|
48 |
|
|
begin
|
49 |
|
|
case rs_index is
|
50 |
|
|
when "000000" => reg_source_out <= ZERO;
|
51 |
|
|
when "000001" => reg_source_out <= reg01;
|
52 |
|
|
when "000010" => reg_source_out <= reg02;
|
53 |
|
|
when "000011" => reg_source_out <= reg03;
|
54 |
|
|
when "000100" => reg_source_out <= reg04;
|
55 |
|
|
when "000101" => reg_source_out <= reg05;
|
56 |
|
|
when "000110" => reg_source_out <= reg06;
|
57 |
|
|
when "000111" => reg_source_out <= reg07;
|
58 |
|
|
when "001000" => reg_source_out <= reg08;
|
59 |
|
|
when "001001" => reg_source_out <= reg09;
|
60 |
|
|
when "001010" => reg_source_out <= reg10;
|
61 |
|
|
when "001011" => reg_source_out <= reg11;
|
62 |
|
|
when "001100" => reg_source_out <= reg12;
|
63 |
|
|
when "001101" => reg_source_out <= reg13;
|
64 |
|
|
when "001110" => reg_source_out <= reg14;
|
65 |
|
|
when "001111" => reg_source_out <= reg15;
|
66 |
|
|
when "010000" => reg_source_out <= reg16;
|
67 |
|
|
when "010001" => reg_source_out <= reg17;
|
68 |
|
|
when "010010" => reg_source_out <= reg18;
|
69 |
|
|
when "010011" => reg_source_out <= reg19;
|
70 |
|
|
when "010100" => reg_source_out <= reg20;
|
71 |
|
|
when "010101" => reg_source_out <= reg21;
|
72 |
|
|
when "010110" => reg_source_out <= reg22;
|
73 |
|
|
when "010111" => reg_source_out <= reg23;
|
74 |
|
|
when "011000" => reg_source_out <= reg24;
|
75 |
|
|
when "011001" => reg_source_out <= reg25;
|
76 |
|
|
when "011010" => reg_source_out <= reg26;
|
77 |
|
|
when "011011" => reg_source_out <= reg27;
|
78 |
|
|
when "011100" => reg_source_out <= reg28;
|
79 |
|
|
when "011101" => reg_source_out <= reg29;
|
80 |
|
|
when "011110" => reg_source_out <= reg30;
|
81 |
|
|
when "011111" => reg_source_out <= reg31;
|
82 |
|
|
when "101100" => reg_source_out <= ZERO(31 downto 1) & reg_status;
|
83 |
|
|
when "101110" => reg_source_out <= reg_epc; --CP0 14
|
84 |
|
|
when "111111" => reg_source_out <= '1' & ZERO(30 downto 0); --intr vector
|
85 |
|
|
when others => reg_source_out <= ZERO;
|
86 |
|
|
end case;
|
87 |
|
|
|
88 |
|
|
case rt_index is
|
89 |
|
|
when "000000" => reg_target_out <= ZERO;
|
90 |
|
|
when "000001" => reg_target_out <= reg01;
|
91 |
|
|
when "000010" => reg_target_out <= reg02;
|
92 |
|
|
when "000011" => reg_target_out <= reg03;
|
93 |
|
|
when "000100" => reg_target_out <= reg04;
|
94 |
|
|
when "000101" => reg_target_out <= reg05;
|
95 |
|
|
when "000110" => reg_target_out <= reg06;
|
96 |
|
|
when "000111" => reg_target_out <= reg07;
|
97 |
|
|
when "001000" => reg_target_out <= reg08;
|
98 |
|
|
when "001001" => reg_target_out <= reg09;
|
99 |
|
|
when "001010" => reg_target_out <= reg10;
|
100 |
|
|
when "001011" => reg_target_out <= reg11;
|
101 |
|
|
when "001100" => reg_target_out <= reg12;
|
102 |
|
|
when "001101" => reg_target_out <= reg13;
|
103 |
|
|
when "001110" => reg_target_out <= reg14;
|
104 |
|
|
when "001111" => reg_target_out <= reg15;
|
105 |
|
|
when "010000" => reg_target_out <= reg16;
|
106 |
|
|
when "010001" => reg_target_out <= reg17;
|
107 |
|
|
when "010010" => reg_target_out <= reg18;
|
108 |
|
|
when "010011" => reg_target_out <= reg19;
|
109 |
|
|
when "010100" => reg_target_out <= reg20;
|
110 |
|
|
when "010101" => reg_target_out <= reg21;
|
111 |
|
|
when "010110" => reg_target_out <= reg22;
|
112 |
|
|
when "010111" => reg_target_out <= reg23;
|
113 |
|
|
when "011000" => reg_target_out <= reg24;
|
114 |
|
|
when "011001" => reg_target_out <= reg25;
|
115 |
|
|
when "011010" => reg_target_out <= reg26;
|
116 |
|
|
when "011011" => reg_target_out <= reg27;
|
117 |
|
|
when "011100" => reg_target_out <= reg28;
|
118 |
|
|
when "011101" => reg_target_out <= reg29;
|
119 |
|
|
when "011110" => reg_target_out <= reg30;
|
120 |
|
|
when "011111" => reg_target_out <= reg31;
|
121 |
|
|
when others => reg_target_out <= ZERO;
|
122 |
|
|
end case;
|
123 |
|
|
|
124 |
|
|
if rising_edge(clk) then
|
125 |
|
|
-- assert reg_dest_new'last_event >= 10 ns
|
126 |
|
|
-- report "Reg_dest timing error";
|
127 |
|
|
case rd_index is
|
128 |
|
|
when "000001" => reg01 <= reg_dest_new;
|
129 |
|
|
when "000010" => reg02 <= reg_dest_new;
|
130 |
|
|
when "000011" => reg03 <= reg_dest_new;
|
131 |
|
|
when "000100" => reg04 <= reg_dest_new;
|
132 |
|
|
when "000101" => reg05 <= reg_dest_new;
|
133 |
|
|
when "000110" => reg06 <= reg_dest_new;
|
134 |
|
|
when "000111" => reg07 <= reg_dest_new;
|
135 |
|
|
when "001000" => reg08 <= reg_dest_new;
|
136 |
|
|
when "001001" => reg09 <= reg_dest_new;
|
137 |
|
|
when "001010" => reg10 <= reg_dest_new;
|
138 |
|
|
when "001011" => reg11 <= reg_dest_new;
|
139 |
|
|
when "001100" => reg12 <= reg_dest_new;
|
140 |
|
|
when "001101" => reg13 <= reg_dest_new;
|
141 |
|
|
when "001110" => reg14 <= reg_dest_new;
|
142 |
|
|
when "001111" => reg15 <= reg_dest_new;
|
143 |
|
|
when "010000" => reg16 <= reg_dest_new;
|
144 |
|
|
when "010001" => reg17 <= reg_dest_new;
|
145 |
|
|
when "010010" => reg18 <= reg_dest_new;
|
146 |
|
|
when "010011" => reg19 <= reg_dest_new;
|
147 |
|
|
when "010100" => reg20 <= reg_dest_new;
|
148 |
|
|
when "010101" => reg21 <= reg_dest_new;
|
149 |
|
|
when "010110" => reg22 <= reg_dest_new;
|
150 |
|
|
when "010111" => reg23 <= reg_dest_new;
|
151 |
|
|
when "011000" => reg24 <= reg_dest_new;
|
152 |
|
|
when "011001" => reg25 <= reg_dest_new;
|
153 |
|
|
when "011010" => reg26 <= reg_dest_new;
|
154 |
|
|
when "011011" => reg27 <= reg_dest_new;
|
155 |
|
|
when "011100" => reg28 <= reg_dest_new;
|
156 |
|
|
when "011101" => reg29 <= reg_dest_new;
|
157 |
|
|
when "011110" => reg30 <= reg_dest_new;
|
158 |
|
|
when "011111" => reg31 <= reg_dest_new;
|
159 |
|
|
when "101100" => reg_status <= reg_dest_new(0);
|
160 |
|
|
when "101110" => reg_epc <= reg_dest_new; --CP0 14
|
161 |
|
|
reg_status <= '0'; --disable interrupts
|
162 |
|
|
when others =>
|
163 |
|
|
end case;
|
164 |
|
|
end if;
|
165 |
|
|
intr_enable <= reg_status;
|
166 |
|
|
end process;
|
167 |
|
|
|
168 |
|
|
end; --architecture logic
|
169 |
|
|
|