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[/] [plasma/] [trunk/] [tools/] [ddr_init.c] - Blame information for rev 406

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1 268 rhoads
/*--------------------------------------------------------------------
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 * TITLE: Plasma DDR Initialization
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 * AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
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 * DATE CREATED: 12/17/05
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 * FILENAME: ddr_init.c
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 * PROJECT: Plasma CPU core
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 * COPYRIGHT: Software placed into the public domain by the author.
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 *    Software 'as is' without warranty.  Author liable for nothing.
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 * DESCRIPTION:
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 *    Plasma DDR Initialization
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 *    Supports 64MB (512Mb) MT46V32M16 by default.
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 *    For 32 MB and 128 MB DDR parts change AddressLines and Bank shift:
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 *    For 32 MB change 13->12 and 11->10.  MT46V16M16
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 *    For 128 MB change 13->14 and 11->12. MT46V64M16
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 *--------------------------------------------------------------------*/
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#define DDR_BASE 0x10000000
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#define MemoryRead(A) (*(volatile int*)(A))
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#define MemoryWrite(A,V) *(volatile int*)(A)=(V)
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extern int putchar(int value);
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extern int puts(const char *string);
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extern void print_hex(unsigned long num);
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//SD_A  <= address_reg(25 downto 13);  --address row
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//SD_BA <= address_reg(12 downto 11);  --bank_address
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//cmd   := address_reg(6 downto 4);    --bits RAS & CAS & WE
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int DdrInitData[] = {
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// AddressLines    Bank        Command
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   (0x000 << 13) | (0 << 11) | (7 << 4),  //CKE=1; NOP="111"
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   (0x400 << 13) | (0 << 11) | (2 << 4),  //A10=1; PRECHARGE ALL="010"
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#ifndef DLL_DISABLE
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   (0x000 << 13) | (1 << 11) | (0 << 4),  //enable DLL; BA="01"; LMR="000"
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#else
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   (0x001 << 13) | (1 << 11) | (0 << 4),  //disable DLL; BA="01"; LMR="000"
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#endif
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   (0x121 << 13) | (0 << 11) | (0 << 4),  //reset DLL, CL=2, BL=2; LMR="000"
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   (0x400 << 13) | (0 << 11) | (2 << 4),  //A10=1; PRECHARGE ALL="010" 
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   (0x000 << 13) | (0 << 11) | (1 << 4),  //AUTO REFRESH="001"
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   (0x000 << 13) | (0 << 11) | (1 << 4),  //AUTO REFRESH="001
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   (0x021 << 13) | (0 << 11) | (0 << 4)   //clear DLL, CL=2, BL=2; LMR="000"
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};
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int DdrInit(void)
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{
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   int i, j, k=0;
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   for(i = 0; i < sizeof(DdrInitData)/sizeof(int); ++i)
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   {
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      MemoryWrite(DDR_BASE + DdrInitData[i], 0);
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      for(j = 0; j < 4; ++j)
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         ++k;
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   }
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   for(j = 0; j < 100; ++j)
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      ++k;
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   k += MemoryRead(DDR_BASE);  //Enable DDR
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   return k;
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}
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#ifdef DDR_TEST_MAIN
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int main()
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{
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   volatile int *ptr = (int*)DDR_BASE;
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   int i;
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   DdrInit();
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   ptr[0] = 0x12345678;
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   if(ptr[0] != 0x12345678)
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      putchar('X');
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   for(i = 0; i < 10; ++i)
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   {
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      ptr[i] = i;
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   }
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   for(i = 0; i < 10; ++i)
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   {
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      if(ptr[i] != i)
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         putchar('A' + i);
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   }
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   *(unsigned char*)DDR_BASE = 0x23;
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   *(unsigned char*)(DDR_BASE+1) = 0x45;
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   *(unsigned char*)(DDR_BASE+2) = 0x67;
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   *(unsigned char*)(DDR_BASE+3) = 0x89;
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   if(ptr[0] != 0x23456789)
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      putchar('Y');
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   puts("\r\ndone\r\n");
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   return 0;
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}
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#endif

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