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[/] [plasma/] [trunk/] [vhdl/] [build_dir/] [Makefile] - Blame information for rev 407

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1 371 rhoads
# Makefile for Plasma on the s3Esk
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# For Linux development environment using free GHDL simulator and
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# Xilinx synthesis tools.
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# Derives from the DDRSDRAM-on-s3Esk makefile
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#
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# This makefile was created by me, Dan Clemmensen. I hereby place it in
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# the public domain, releasing any rights. I retain the right to re-use
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# this work as the basis for a derived work.
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#
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# Use GHDL for simulation, and then use the Xilinx tools in batch mode for
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# synthesis and download.
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# Before you use this makefile for the first time, you will need to build
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# the plasma tools.  After that, you can do the rest of the development
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# using this makefile, unless you change a tool.
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# Place this makefile and the associated ISE_scripts directory in a
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# subdirectory of the VHDL directory.  We use this approach because the Xilinx
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# tools create a large number of temporary files in the working directory.
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#
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# Usage:
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# make clean    # removes derived files and directories
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# make load     # builds everthing from scratch and
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#               #   loads the flash mem on the target
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# make simtest  # builds and runs as a GHDL simulation
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# make view     # displays the results of the simulation
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# To help isolate problems, you may run a series of steps instead of the whole
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# "make load." Look below to see them.
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# VHDL_DIR is the top-level VHDL directory for Plasma.
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VHDL_DIR = ..
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# PROJ_VHDL comprises files used in both the actual target and the sim
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PROJ_VHDL = \
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      $(VHDL_DIR)/mlite_pack.vhd \
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      $(VHDL_DIR)/plasma_3e.vhd \
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      $(VHDL_DIR)/ddr_ctrl.vhd \
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      $(VHDL_DIR)/plasma.vhd \
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      generated/ram_image.vhd \
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      $(VHDL_DIR)/uart.vhd \
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      $(VHDL_DIR)/eth_dma.vhd \
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      $(VHDL_DIR)/mlite_cpu.vhd \
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      $(VHDL_DIR)/alu.vhd \
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      $(VHDL_DIR)/bus_mux.vhd \
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      $(VHDL_DIR)/control.vhd \
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      $(VHDL_DIR)/mem_ctrl.vhd \
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      $(VHDL_DIR)/mult.vhd \
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      $(VHDL_DIR)/pipeline.vhd \
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      $(VHDL_DIR)/pc_next.vhd \
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      $(VHDL_DIR)/reg_bank.vhd \
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      $(VHDL_DIR)/shifter.vhd \
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      $(VHDL_DIR)/cache.vhd
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# TARGET_VHDL comprises files used on the target but not in sim
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TARGET_VHDL =
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# SIM_VHDL comprises files used in sim but not on the target
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# for this  sim, these simulate the rest of the S3Esk board
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SIM_DIR = $(VHDL_DIR)/simulation
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SIM_VHDL = \
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      $(VHDL_DIR)/mt46v16m16.vhd \
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      $(VHDL_DIR)/tbench.vhd
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SIM_TOP = tbench
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GCC_PARAMS=
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OBJS = $(VHDL:.vhd=.o)
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# GHDL config
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OBJDIR = obj
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ISE_DIR=/opt/Xilinx/11.1/ISE
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GHDL_LIBS = $(ISE_DIR)/ghdl/unisim
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GHDL_FLAGS = --ieee=synopsys -fexplicit -P$(GHDL_LIBS)
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GHDL_FLAGS += --workdir=$(OBJDIR) --warn-no-vital-generic
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%.o: %.vhd
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        ghdl -a $(GHDL_FLAGS) $<
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all: simtest
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old:  workdir $(OBJS)
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# invocation strings for helper tools to build Xilinx BRAM memory images.
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TOOLS = ../../tools
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# generate the ram_image.vhd
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generated:
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        rm -rf generated
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        mkdir generated
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        $(TOOLS)/ram_image.exe $(VHDL_DIR)/ram_xilinx.vhd $(TOOLS)/code.txt generated/ram_image.vhd
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NAME=main
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workdir:
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        mkdir -p $(OBJDIR)
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clean:
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        rm -rf *.o *.cf $(OBJDIR) tb *.vcd main $(SIM_TOP) *.ghw
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        rm -f *.bit *.bgn *_pad.txt *_pad.csv *.xpi *.srp *.ngc *.par
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        rm -f *.lst *.ngd *.ngm *.pcf *.mrp *.unroutes *.pad
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        rm -f *.bld *.ncd *.twr *.drc
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        rm -rf xst $(NAME).prj
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        rm -rf generated
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simtest: workdir generated
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        ghdl -i $(GHDL_FLAGS) $(PROJ_VHDL) $(SIM_VHDL)
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        ghdl -m $(GHDL_FLAGS) $(SIM_TOP)
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sim:
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        ghdl -r $(SIM_TOP) --stop-time=10ms --wave=generated/out.ghw 2> /dev/null
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view:
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        gtkwave generated/out.ghw view.sav
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#Xilinx ISE actions. Uses a wrapper script named "xilinx" to run the ISE batch commands
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# create an ISE project file from the list of VHDL files
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$(NAME).prj: $(PROJ_VHDL) $(TARGET_VHDL)
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        echo $(PROJ_VHDL) $(TARGET_VHDL)|tr " " "\n">$(NAME).prj
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bitfile:  generated step0 step1 step2 step3 step4 step5
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step0: $(NAME).prj
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        xilinx xst -ifn ISE_scripts/$(NAME).scrs -ofn $(NAME).srp
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step1:
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        xilinx ngdbuild -nt on -uc ../spartan3e.ucf $(NAME).ngc $(NAME).ngd
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step2:
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        xilinx map -pr b $(NAME).ngd -o $(NAME).ncd $(NAME).pcf
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step3:
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        xilinx par -w -ol high $(NAME).ncd $(NAME).ncd $(NAME).pcf
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step4:
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        xilinx trce -v 10 -o $(NAME).twr $(NAME).ncd $(NAME).pcf
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step5:
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        xilinx bitgen $(NAME).ncd generated/$(NAME).bit -w #-f $(NAME).ut
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generated/main.bit: bitfile
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mcs:  generated/main.bit
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        xilinx impact -batch ISE_scripts/makeprom.cmds
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generated/main.mcs: mcs
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load: generated/main.mcs
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        xilinx impact -batch ISE_scripts/loadprom.cmds
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impact:
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        xilinx impact
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ise: $(NAME).prj
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        xilinx ise

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