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[/] [plasma/] [trunk/] [vhdl/] [cache.vhd] - Blame information for rev 406

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---------------------------------------------------------------------
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-- TITLE: Cache Controller
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-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
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-- DATE CREATED: 12/22/08
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-- FILENAME: cache.vhd
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-- PROJECT: Plasma CPU core
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-- COPYRIGHT: Software placed into the public domain by the author.
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--    Software 'as is' without warranty.  Author liable for nothing.
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-- DESCRIPTION:
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--    Control 4KB unified cache that uses the upper 4KB of the 8KB
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--    internal RAM.  Only lowest 2MB of DDR is cached.
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--    Only include file for Xilinx FPGAs.
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---------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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library UNISIM;
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use UNISIM.vcomponents.all;
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use work.mlite_pack.all;
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entity cache is
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   generic(memory_type : string := "DEFAULT");
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   port(clk            : in std_logic;
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        reset          : in std_logic;
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        address_next   : in std_logic_vector(31 downto 2);
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        byte_we_next   : in std_logic_vector(3 downto 0);
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        cpu_address    : in std_logic_vector(31 downto 2);
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        mem_busy       : in std_logic;
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        cache_access   : out std_logic;   --access 4KB cache
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        cache_checking : out std_logic;   --checking if cache hit
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        cache_miss     : out std_logic);  --cache miss
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end; --cache
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architecture logic of cache is
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   subtype state_type is std_logic_vector(1 downto 0);
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   constant STATE_IDLE     : state_type := "00";
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   constant STATE_CHECKING : state_type := "01";
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   constant STATE_MISSED   : state_type := "10";
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   constant STATE_WAITING  : state_type := "11";
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   signal state_reg        : state_type;
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   signal state            : state_type;
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   signal state_next       : state_type;
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   signal cache_address    : std_logic_vector(10 downto 0);
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   signal cache_tag_in     : std_logic_vector(8 downto 0);
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   signal cache_tag_reg    : std_logic_vector(8 downto 0);
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   signal cache_tag_out    : std_logic_vector(8 downto 0);
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   signal cache_we         : std_logic;
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begin
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   cache_proc: process(clk, reset, mem_busy, cache_address,
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      state_reg, state, state_next,
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      address_next, byte_we_next, cache_tag_in, --Stage1
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      cache_tag_reg, cache_tag_out,             --Stage2
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      cpu_address) --Stage3
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   begin
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      case state_reg is
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      when STATE_IDLE =>            --cache idle
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         cache_checking <= '0';
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         cache_miss <= '0';
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         state <= STATE_IDLE;
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      when STATE_CHECKING =>        --current read in cached range, check if match
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         cache_checking <= '1';
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         if cache_tag_out /= cache_tag_reg or cache_tag_out = ONES(8 downto 0) then
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            cache_miss <= '1';
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            state <= STATE_MISSED;
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         else
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            cache_miss <= '0';
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            state <= STATE_IDLE;
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         end if;
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      when STATE_MISSED =>          --current read cache miss
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         cache_checking <= '0';
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         cache_miss <= '1';
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         if mem_busy = '1' then
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            state <= STATE_MISSED;
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         else
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            state <= STATE_WAITING;
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         end if;
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      when STATE_WAITING =>         --waiting for memory access to complete
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         cache_checking <= '0';
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         cache_miss <= '0';
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         if mem_busy = '1' then
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            state <= STATE_WAITING;
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         else
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            state <= STATE_IDLE;
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         end if;
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      when others =>
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         cache_checking <= '0';
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         cache_miss <= '0';
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         state <= STATE_IDLE;
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      end case; --state
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      if state = STATE_IDLE then    --check if next access in cached range
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         cache_address <= '0' & address_next(11 downto 2);
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         if address_next(30 downto 21) = "0010000000" then  --first 2MB of DDR
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            cache_access <= '1';
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            if byte_we_next = "0000" then     --read cycle
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               cache_we <= '0';
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               state_next <= STATE_CHECKING;  --need to check if match
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            else
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               cache_we <= '1';               --update cache tag
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               state_next <= STATE_WAITING;
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            end if;
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         else
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            cache_access <= '0';
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            cache_we <= '0';
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            state_next <= STATE_IDLE;
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         end if;
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      else
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         cache_address <= '0' & cpu_address(11 downto 2);
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         cache_access <= '0';
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         if state = STATE_MISSED then
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            cache_we <= '1';                  --update cache tag
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         else
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            cache_we <= '0';
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         end if;
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         state_next <= state;
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      end if;
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      if byte_we_next = "0000" or byte_we_next = "1111" then  --read or 32-bit write
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         cache_tag_in <= address_next(20 downto 12);
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      else
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         cache_tag_in <= ONES(8 downto 0);  --invalid tag
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      end if;
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      if reset = '1' then
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         state_reg <= STATE_IDLE;
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         cache_tag_reg <= ZERO(8 downto 0);
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      elsif rising_edge(clk) then
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         state_reg <= state_next;
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         if state = STATE_IDLE and state_reg /= STATE_MISSED then
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            cache_tag_reg <= cache_tag_in;
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         end if;
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      end if;
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   end process;
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   cache_xilinx: if memory_type = "XILINX_16X" generate
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   begin
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      cache_tag: RAMB16_S9  --Xilinx specific
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      port map (
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         DO   => cache_tag_out(7 downto 0),
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         DOP  => cache_tag_out(8 downto 8),
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         ADDR => cache_address,             --registered
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         CLK  => clk,
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         DI   => cache_tag_in(7 downto 0),  --registered
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         DIP  => cache_tag_in(8 downto 8),
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         EN   => '1',
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         SSR  => ZERO(0),
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         WE   => cache_we);
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   end generate; --cache_xilinx
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   cache_generic: if memory_type /= "XILINX_16X" generate
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   begin
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      cache_tag: process(clk, cache_address, cache_tag_in, cache_we)
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         constant ADDRESS_WIDTH : natural := 10;
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         type storage_array is
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            array(natural range 0 to 2 ** ADDRESS_WIDTH - 1) of
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            std_logic_vector(8 downto 0);
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         variable storage : storage_array;
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         variable index   : natural := 0;
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      begin
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         if rising_edge(clk) then
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            index := conv_integer(cache_address(ADDRESS_WIDTH-1 downto 0));
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            if cache_we = '1' then
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               storage(index) := cache_tag_in;
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            end if;
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            cache_tag_out <= storage(index);
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         end if;
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      end process; --cache_tag
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   end generate; --cache_generic
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end; --logic
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