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[/] [plasma/] [trunk/] [vhdl/] [eth_dma.vhd] - Blame information for rev 406

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1 288 rhoads
---------------------------------------------------------------------
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-- TITLE: Ethernet DMA
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-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
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-- DATE CREATED: 12/27/07
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-- FILENAME: eth_dma.vhd
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-- PROJECT: Plasma CPU core
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-- COPYRIGHT: Software placed into the public domain by the author.
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--    Software 'as is' without warranty.  Author liable for nothing.
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-- DESCRIPTION:
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--    Ethernet DMA (Direct Memory Access) controller.  
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--    Reads four bits and writes four bits from/to the Ethernet PHY each 
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--    2.5 MHz clock cycle.  Received data is DMAed starting at 0x13ff0000 
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--    transmit data is read from 0x13fd0000.
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--    To send a packet write bytes/4 to Ethernet send register.
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---------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use work.mlite_pack.all;
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entity eth_dma is port(
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   clk         : in std_logic;                      --25 MHz
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   reset       : in std_logic;
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   enable_eth  : in std_logic;                      --enable receive DMA
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   select_eth  : in std_logic;
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   rec_isr     : out std_logic;                     --data received
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   send_isr    : out std_logic;                     --transmit done
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   address     : out std_logic_vector(31 downto 2); --to DDR
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   byte_we     : out std_logic_vector(3 downto 0);
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   data_write  : out std_logic_vector(31 downto 0);
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   data_read   : in std_logic_vector(31 downto 0);
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   pause_in    : in std_logic;
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   mem_address : in std_logic_vector(31 downto 2);  --from CPU
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   mem_byte_we : in std_logic_vector(3 downto 0);
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   data_w      : in std_logic_vector(31 downto 0);
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   pause_out   : out std_logic;
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   E_RX_CLK    : in std_logic;                      --2.5 MHz receive
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   E_RX_DV     : in std_logic;                      --data valid
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   E_RXD       : in std_logic_vector(3 downto 0);   --receive nibble
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   E_TX_CLK    : in std_logic;                      --2.5 MHz transmit
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   E_TX_EN     : out std_logic;                     --transmit enable
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   E_TXD       : out std_logic_vector(3 downto 0)); --transmit nibble
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end; --entity eth_dma
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architecture logic of eth_dma is
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   signal rec_clk    : std_logic_vector(1 downto 0);  --receive
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   signal rec_store  : std_logic_vector(31 downto 0); --to DDR
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   signal rec_data   : std_logic_vector(27 downto 0);
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   signal rec_cnt    : std_logic_vector(2 downto 0);  --nibbles
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   signal rec_words  : std_logic_vector(13 downto 0);
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   signal rec_dma    : std_logic_vector(1 downto 0);  --active & request
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   signal rec_done   : std_logic;
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   signal send_clk   : std_logic_vector(1 downto 0);  --transmit
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   signal send_read  : std_logic_vector(31 downto 0); --from DDR
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   signal send_data  : std_logic_vector(31 downto 0);
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   signal send_cnt   : std_logic_vector(2 downto 0);  --nibbles
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   signal send_words : std_logic_vector(8 downto 0);
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   signal send_level : std_logic_vector(8 downto 0);
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   signal send_dma   : std_logic_vector(1 downto 0);  --active & request
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   signal send_enable: std_logic;
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begin  --architecture
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   dma_proc: process(clk, reset, enable_eth, select_eth,
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         data_read, pause_in, mem_address, mem_byte_we, data_w,
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         E_RX_CLK, E_RX_DV, E_RXD, E_TX_CLK,
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         rec_clk, rec_store, rec_data,
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         rec_cnt, rec_words, rec_dma, rec_done,
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         send_clk, send_read, send_data, send_cnt, send_words,
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         send_level, send_dma, send_enable)
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   begin
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      if reset = '1' then
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         rec_clk <= "00";
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         rec_cnt <= "000";
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         rec_words <= ZERO(13 downto 0);
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         rec_dma <= "00";
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         rec_done <= '0';
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         send_clk <= "00";
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         send_cnt <= "000";
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         send_words <= ZERO(8 downto 0);
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         send_level <= ZERO(8 downto 0);
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         send_dma <= "00";
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         send_enable <= '0';
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      elsif rising_edge(clk) then
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         --Receive nibble on low->high E_RX_CLK.  Send to DDR every 32 bits.
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         rec_clk <= rec_clk(0) & E_RX_CLK;
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         if rec_clk = "01" and enable_eth = '1' then
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            if E_RX_DV = '1' or rec_cnt /= "000" then
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               if rec_cnt = "111" then
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                  rec_store <= rec_data & E_RXD;
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                  rec_dma(0) <= '1';           --request DMA
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               end if;
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               rec_data <= rec_data(23 downto 0) & E_RXD;
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               rec_cnt <= rec_cnt + 1;
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            end if;
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         end if;
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         --Set transmit count or clear receive interrupt
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         if select_eth = '1' then
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            if mem_byte_we /= "0000" then
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               send_cnt <= "000";
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               send_words <= ZERO(8 downto 0);
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               send_level <= data_w(8 downto 0);
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               send_dma(0) <= '1';
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            else
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               rec_done <= '0';
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            end if;
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         end if;
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         --Transmit nibble on low->high E_TX_CLK.  Get 32 bits from DDR.
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         send_clk <= send_clk(0) & E_TX_CLK;
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         if send_clk = "01" then
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            if send_cnt = "111" then
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               if send_words /= send_level then
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                  send_data <= send_read;
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                  send_dma(0) <= '1';
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                  send_enable <= '1';
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               else
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                  send_enable <= '0';
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               end if;
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            else
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               send_data(31 downto 4) <= send_data(27 downto 0);
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            end if;
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            send_cnt <= send_cnt + 1;
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         end if;
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         --Pick which type of DMA operation: bit0 = request; bit1 = active
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         if pause_in = '0' then
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            if rec_dma(1) = '1' then
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               rec_dma <= "00";               --DMA done
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               rec_words <= rec_words + 1;
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               if E_RX_DV = '0' then
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                  rec_done <= '1';
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               end if;
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            elsif send_dma(1) = '1' then
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               send_dma <= "00";
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               send_words <= send_words + 1;
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               send_read <= data_read;
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            elsif rec_dma(0) = '1' then
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               rec_dma(1) <= '1';             --start DMA
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            elsif send_dma(0) = '1' then
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               send_dma(1) <= '1';            --start DMA
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            end if;
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         end if;
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      end if;  --rising_edge(clk)
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      E_TXD <= send_data(31 downto 28);
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      E_TX_EN <= send_enable;
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      rec_isr <= rec_done;
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      if send_words = send_level then
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         send_isr <= '1';
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      else
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         send_isr <= '0';
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      end if;
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      if rec_dma(1) = '1' then
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         address <= "0001001111111111" & rec_words;        --0x13ff0000
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         byte_we <= "1111";
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         data_write <= rec_store;
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         pause_out <= '1';                                 --to CPU
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      elsif send_dma(1) = '1' then
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         address <= "000100111111111000000" & send_words;  --0x13fe0000
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         byte_we <= "0000";
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         data_write <= data_w;
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         pause_out <= '1';
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      else
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         address <= mem_address;  --Send request from CPU to DDR
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         byte_we <= mem_byte_we;
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         data_write <= data_w;
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         pause_out <= '0';
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      end if;
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   end process;
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end; --architecture logic

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