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---------------------------------------------------------------------
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-- TITLE: Plasma CPU core
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-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
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-- DATE CREATED: 2/15/01
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-- FILENAME: mlite_cpu.vhd
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-- PROJECT: Plasma CPU core
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-- COPYRIGHT: Software placed into the public domain by the author.
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--    Software 'as is' without warranty.  Author liable for nothing.
9
-- NOTE:  MIPS(tm) and MIPS I(tm) are registered trademarks of MIPS 
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--    Technologies.  MIPS Technologies does not endorse and is not 
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--    associated with this project.
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-- DESCRIPTION:
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--    Top level VHDL document that ties the nine other entities together.
14
--
15
-- Executes all MIPS I(tm) opcodes but exceptions and non-aligned
16
-- memory accesses.  Based on information found in:
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--    "MIPS RISC Architecture" by Gerry Kane and Joe Heinrich
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--    and "The Designer's Guide to VHDL" by Peter J. Ashenden
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--
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-- The CPU is implemented as a two or three stage pipeline.
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-- An add instruction would take the following steps (see cpu.gif):
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-- Stage #0:
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--    1.  The "pc_next" entity passes the program counter (PC) to the 
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--        "mem_ctrl" entity which fetches the opcode from memory.
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-- Stage #1:
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--    2.  The memory returns the opcode.
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-- Stage #2:
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--    3.  "Mem_ctrl" passes the opcode to the "control" entity.
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--    4.  "Control" converts the 32-bit opcode to a 60-bit VLWI opcode
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--        and sends control signals to the other entities.
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--    5.  Based on the rs_index and rt_index control signals, "reg_bank" 
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--        sends the 32-bit reg_source and reg_target to "bus_mux".
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--    6.  Based on the a_source and b_source control signals, "bus_mux"
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--        multiplexes reg_source onto a_bus and reg_target onto b_bus.
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-- Stage #3 (part of stage #2 if using two stage pipeline):
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--    7.  Based on the alu_func control signals, "alu" adds the values
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--        from a_bus and b_bus and places the result on c_bus.
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--    8.  Based on the c_source control signals, "bus_bux" multiplexes
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--        c_bus onto reg_dest.
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--    9.  Based on the rd_index control signal, "reg_bank" saves
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--        reg_dest into the correct register.
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-- Stage #3b:
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--   10.  Read or write memory if needed.
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--
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-- All signals are active high. 
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-- Here are the signals for writing a character to address 0xffff
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-- when using a two stage pipeline:
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--
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-- Program:
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-- addr     value  opcode 
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-- =============================
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--   3c: 00000000  nop
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--   40: 34040041  li $a0,0x41
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--   44: 3405ffff  li $a1,0xffff
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--   48: a0a40000  sb $a0,0($a1)
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--   4c: 00000000  nop
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--   50: 00000000  nop
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--
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--      intr_in                             mem_pause 
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--  reset_in                               byte_we     Stages
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--     ns         address     data_w     data_r        40 44 48 4c 50
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--   3600  0  0  00000040   00000000   34040041  0  0   1  
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--   3700  0  0  00000044   00000000   3405FFFF  0  0   2  1  
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--   3800  0  0  00000048   00000000   A0A40000  0  0      2  1  
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--   3900  0  0  0000004C   41414141   00000000  0  0         2  1
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--   4000  0  0  0000FFFC   41414141   XXXXXX41  1  0         3  2  
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--   4100  0  0  00000050   00000000   00000000  0  0               1
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---------------------------------------------------------------------
69
library ieee;
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use work.mlite_pack.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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74
entity mlite_cpu is
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   generic(memory_type     : string  := "XILINX_16X"; --ALTERA_LPM, or DUAL_PORT_
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           mult_type       : string  := "DEFAULT"; --AREA_OPTIMIZED
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           shifter_type    : string  := "DEFAULT"; --AREA_OPTIMIZED
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           alu_type        : string  := "DEFAULT"; --AREA_OPTIMIZED
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           pipeline_stages : natural := 2); --2 or 3
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   port(clk          : in std_logic;
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        reset_in     : in std_logic;
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        intr_in      : in std_logic;
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        address_next : out std_logic_vector(31 downto 2); --for synch ram
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        byte_we_next : out std_logic_vector(3 downto 0);
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87
        address      : out std_logic_vector(31 downto 2);
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        byte_we      : out std_logic_vector(3 downto 0);
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        data_w       : out std_logic_vector(31 downto 0);
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        data_r       : in std_logic_vector(31 downto 0);
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        mem_pause    : in std_logic);
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end; --entity mlite_cpu
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94
architecture logic of mlite_cpu is
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   --When using a two stage pipeline "sigD <= sig".
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   --When using a three stage pipeline "sigD <= sig when rising_edge(clk)",
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   --  so sigD is delayed by one clock cycle.
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   signal opcode         : std_logic_vector(31 downto 0);
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   signal rs_index       : std_logic_vector(5 downto 0);
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   signal rt_index       : std_logic_vector(5 downto 0);
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   signal rd_index       : std_logic_vector(5 downto 0);
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   signal rd_indexD      : std_logic_vector(5 downto 0);
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   signal reg_source     : std_logic_vector(31 downto 0);
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   signal reg_target     : std_logic_vector(31 downto 0);
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   signal reg_dest       : std_logic_vector(31 downto 0);
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   signal reg_destD      : std_logic_vector(31 downto 0);
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   signal a_bus          : std_logic_vector(31 downto 0);
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   signal a_busD         : std_logic_vector(31 downto 0);
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   signal b_bus          : std_logic_vector(31 downto 0);
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   signal b_busD         : std_logic_vector(31 downto 0);
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   signal c_bus          : std_logic_vector(31 downto 0);
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   signal c_alu          : std_logic_vector(31 downto 0);
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   signal c_shift        : std_logic_vector(31 downto 0);
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   signal c_mult         : std_logic_vector(31 downto 0);
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   signal c_memory       : std_logic_vector(31 downto 0);
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   signal imm            : std_logic_vector(15 downto 0);
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   signal pc_future      : std_logic_vector(31 downto 2);
118
   signal pc_current     : std_logic_vector(31 downto 2);
119
   signal pc_plus4       : std_logic_vector(31 downto 2);
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   signal alu_func       : alu_function_type;
121
   signal alu_funcD      : alu_function_type;
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   signal shift_func     : shift_function_type;
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   signal shift_funcD    : shift_function_type;
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   signal mult_func      : mult_function_type;
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   signal mult_funcD     : mult_function_type;
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   signal branch_func    : branch_function_type;
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   signal take_branch    : std_logic;
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   signal a_source       : a_source_type;
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   signal b_source       : b_source_type;
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   signal c_source       : c_source_type;
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   signal pc_source      : pc_source_type;
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   signal mem_source     : mem_source_type;
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   signal pause_mult     : std_logic;
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   signal pause_ctrl     : std_logic;
135
   signal pause_pipeline : std_logic;
136
   signal pause_any      : std_logic;
137
   signal pause_non_ctrl : std_logic;
138
   signal pause_bank     : std_logic;
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   signal nullify_op     : std_logic;
140
   signal intr_enable    : std_logic;
141
   signal intr_signal    : std_logic;
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   signal exception_sig  : std_logic;
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   signal reset_reg      : std_logic_vector(3 downto 0);
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   signal reset          : std_logic;
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begin  --architecture
146
 
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   pause_any <= (mem_pause or pause_ctrl) or (pause_mult or pause_pipeline);
148
   pause_non_ctrl <= (mem_pause or pause_mult) or pause_pipeline;
149
   pause_bank <= (mem_pause or pause_ctrl or pause_mult) and not pause_pipeline;
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   nullify_op <= '1' when (pc_source = FROM_LBRANCH and take_branch = '0')
151 194 rhoads
                          or intr_signal = '1' or exception_sig = '1'
152 124 rhoads
                          else '0';
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   c_bus <= c_alu or c_shift or c_mult;
154 73 rhoads
   reset <= '1' when reset_in = '1' or reset_reg /= "1111" else '0';
155 39 rhoads
 
156 73 rhoads
   --synchronize reset and interrupt pins
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   intr_proc: process(clk, reset_in, reset_reg, intr_in, intr_enable,
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      pc_source, pc_current, pause_any)
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   begin
160
      if reset_in = '1' then
161
         reset_reg <= "0000";
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         intr_signal <= '0';
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      elsif rising_edge(clk) then
164
         if reset_reg /= "1111" then
165
            reset_reg <= reset_reg + 1;
166
         end if;
167 124 rhoads
 
168 73 rhoads
         --don't try to interrupt a multi-cycle instruction
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         if pause_any = '0' then
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            if intr_in = '1' and intr_enable = '1' and
171
                  pc_source = FROM_INC4 then
172
               --the epc will contain pc+4
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               intr_signal <= '1';
174
            else
175
               intr_signal <= '0';
176
            end if;
177 73 rhoads
         end if;
178 124 rhoads
 
179 73 rhoads
      end if;
180
   end process;
181 39 rhoads
 
182
   u1_pc_next: pc_next PORT MAP (
183
        clk          => clk,
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        reset_in     => reset,
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        take_branch  => take_branch,
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        pause_in     => pause_any,
187
        pc_new       => c_bus(31 downto 2),
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        opcode25_0   => opcode(25 downto 0),
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        pc_source    => pc_source,
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        pc_future    => pc_future,
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        pc_current   => pc_current,
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        pc_plus4     => pc_plus4);
193 39 rhoads
 
194 73 rhoads
   u2_mem_ctrl: mem_ctrl
195
      PORT MAP (
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        clk          => clk,
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        reset_in     => reset,
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        pause_in     => pause_non_ctrl,
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        nullify_op   => nullify_op,
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        address_pc   => pc_future,
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        opcode_out   => opcode,
202
 
203 139 rhoads
        address_in   => c_bus,
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        mem_source   => mem_source,
205
        data_write   => reg_target,
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        data_read    => c_memory,
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        pause_out    => pause_ctrl,
208 39 rhoads
 
209 264 rhoads
        address_next => address_next,
210
        byte_we_next => byte_we_next,
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212 264 rhoads
        address      => address,
213
        byte_we      => byte_we,
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        data_w       => data_w,
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        data_r       => data_r);
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   u3_control: control PORT MAP (
218
        opcode       => opcode,
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        intr_signal  => intr_signal,
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        rs_index     => rs_index,
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        rt_index     => rt_index,
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        rd_index     => rd_index,
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        imm_out      => imm,
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        alu_func     => alu_func,
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        shift_func   => shift_func,
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        mult_func    => mult_func,
227
        branch_func  => branch_func,
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        a_source_out => a_source,
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        b_source_out => b_source,
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        c_source_out => c_source,
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        pc_source_out=> pc_source,
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        mem_source_out=> mem_source,
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        exception_out=> exception_sig);
234 39 rhoads
 
235 47 rhoads
   u4_reg_bank: reg_bank
236
      generic map(memory_type => memory_type)
237
      port map (
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        clk            => clk,
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        reset_in       => reset,
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        pause          => pause_bank,
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        rs_index       => rs_index,
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        rt_index       => rt_index,
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        rd_index       => rd_indexD,
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        reg_source_out => reg_source,
245
        reg_target_out => reg_target,
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        reg_dest_new   => reg_destD,
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        intr_enable    => intr_enable);
248
 
249
   u5_bus_mux: bus_mux port map (
250
        imm_in       => imm,
251
        reg_source   => reg_source,
252
        a_mux        => a_source,
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        a_out        => a_bus,
254
 
255
        reg_target   => reg_target,
256
        b_mux        => b_source,
257
        b_out        => b_bus,
258
 
259
        c_bus        => c_bus,
260
        c_memory     => c_memory,
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        c_pc         => pc_current,
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        c_pc_plus4   => pc_plus4,
263
        c_mux        => c_source,
264
        reg_dest_out => reg_dest,
265
 
266 73 rhoads
        branch_func  => branch_func,
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        take_branch  => take_branch);
268
 
269 47 rhoads
   u6_alu: alu
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      generic map (alu_type => alu_type)
271 47 rhoads
      port map (
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        a_in         => a_busD,
273
        b_in         => b_busD,
274
        alu_function => alu_funcD,
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        c_alu        => c_alu);
276
 
277 114 rhoads
   u7_shifter: shifter
278
      generic map (shifter_type => shifter_type)
279
      port map (
280 73 rhoads
        value        => b_busD,
281
        shift_amount => a_busD(4 downto 0),
282
        shift_func   => shift_funcD,
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        c_shift      => c_shift);
284
 
285 47 rhoads
   u8_mult: mult
286 139 rhoads
      generic map (mult_type => mult_type)
287 47 rhoads
      port map (
288 39 rhoads
        clk       => clk,
289 128 rhoads
        reset_in  => reset,
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        a         => a_busD,
291
        b         => b_busD,
292
        mult_func => mult_funcD,
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        c_mult    => c_mult,
294
        pause_out => pause_mult);
295
 
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   pipeline2: if pipeline_stages <= 2 generate
297 73 rhoads
      a_busD <= a_bus;
298
      b_busD <= b_bus;
299
      alu_funcD <= alu_func;
300
      shift_funcD <= shift_func;
301
      mult_funcD <= mult_func;
302
      rd_indexD <= rd_index;
303
      reg_destD <= reg_dest;
304
      pause_pipeline <= '0';
305
   end generate; --pipeline2
306
 
307 202 rhoads
   pipeline3: if pipeline_stages > 2 generate
308
      --When operating in three stage pipeline mode, the following signals
309 73 rhoads
      --are delayed by one clock cycle:  a_bus, b_bus, alu/shift/mult_func,
310
      --c_source, and rd_index.
311
   u9_pipeline: pipeline port map (
312
        clk            => clk,
313
        reset          => reset,
314
        a_bus          => a_bus,
315
        a_busD         => a_busD,
316
        b_bus          => b_bus,
317
        b_busD         => b_busD,
318
        alu_func       => alu_func,
319
        alu_funcD      => alu_funcD,
320
        shift_func     => shift_func,
321
        shift_funcD    => shift_funcD,
322
        mult_func      => mult_func,
323
        mult_funcD     => mult_funcD,
324
        reg_dest       => reg_dest,
325
        reg_destD      => reg_destD,
326
        rd_index       => rd_index,
327
        rd_indexD      => rd_indexD,
328
 
329
        rs_index       => rs_index,
330
        rt_index       => rt_index,
331
        pc_source      => pc_source,
332
        mem_source     => mem_source,
333
        a_source       => a_source,
334
        b_source       => b_source,
335
        c_source       => c_source,
336
        c_bus          => c_bus,
337
        pause_any      => pause_any,
338
        pause_pipeline => pause_pipeline);
339
 
340 202 rhoads
   end generate; --pipeline3
341 139 rhoads
 
342 39 rhoads
end; --architecture logic

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