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[/] [plasma/] [trunk/] [vhdl/] [plasma.vhd] - Blame information for rev 406

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---------------------------------------------------------------------
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-- TITLE: Plasma (CPU core with memory)
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-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
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-- DATE CREATED: 6/4/02
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-- FILENAME: plasma.vhd
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-- PROJECT: Plasma CPU core
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-- COPYRIGHT: Software placed into the public domain by the author.
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--    Software 'as is' without warranty.  Author liable for nothing.
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-- DESCRIPTION:
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--    This entity combines the CPU core with memory and a UART.
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--
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-- Memory Map:
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--   0x00000000 - 0x0000ffff   Internal RAM (8KB)
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--   0x10000000 - 0x100fffff   External RAM (1MB)
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--   Access all Misc registers with 32-bit accesses
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--   0x20000000  Uart Write (will pause CPU if busy)
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--   0x20000000  Uart Read
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--   0x20000010  IRQ Mask
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--   0x20000020  IRQ Status
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--   0x20000030  GPIO0 Out Set bits
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--   0x20000040  GPIO0 Out Clear bits
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--   0x20000050  GPIOA In
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--   0x20000060  Counter
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--   0x20000070  Ethernet transmit count
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--   IRQ bits:
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--      7   GPIO31
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--      6  ^GPIO31
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--      5   EthernetSendDone
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--      4   EthernetReceive
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--      3   Counter(18)
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--      2  ^Counter(18)
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--      1  ^UartWriteBusy
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--      0   UartDataAvailable
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---------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.mlite_pack.all;
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entity plasma is
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   generic(memory_type : string := "XILINX_16X"; --"DUAL_PORT_" "ALTERA_LPM";
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           log_file    : string := "UNUSED";
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           ethernet    : std_logic := '0';
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           use_cache   : std_logic := '0');
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   port(clk          : in std_logic;
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        reset        : in std_logic;
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        uart_write   : out std_logic;
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        uart_read    : in std_logic;
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        address      : out std_logic_vector(31 downto 2);
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        byte_we      : out std_logic_vector(3 downto 0);
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        data_write   : out std_logic_vector(31 downto 0);
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        data_read    : in std_logic_vector(31 downto 0);
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        mem_pause_in : in std_logic;
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        no_ddr_start : out std_logic;
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        no_ddr_stop  : out std_logic;
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        gpio0_out    : out std_logic_vector(31 downto 0);
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        gpioA_in     : in std_logic_vector(31 downto 0));
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end; --entity plasma
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architecture logic of plasma is
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   signal address_next      : std_logic_vector(31 downto 2);
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   signal byte_we_next      : std_logic_vector(3 downto 0);
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   signal cpu_address       : std_logic_vector(31 downto 0);
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   signal cpu_byte_we       : std_logic_vector(3 downto 0);
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   signal cpu_data_w        : std_logic_vector(31 downto 0);
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   signal cpu_data_r        : std_logic_vector(31 downto 0);
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   signal cpu_pause         : std_logic;
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   signal data_read_uart    : std_logic_vector(7 downto 0);
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   signal write_enable      : std_logic;
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   signal eth_pause_in      : std_logic;
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   signal eth_pause         : std_logic;
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   signal mem_busy          : std_logic;
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   signal enable_misc       : std_logic;
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   signal enable_uart       : std_logic;
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   signal enable_uart_read  : std_logic;
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   signal enable_uart_write : std_logic;
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   signal enable_eth        : std_logic;
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   signal gpio0_reg         : std_logic_vector(31 downto 0);
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   signal uart_write_busy   : std_logic;
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   signal uart_data_avail   : std_logic;
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   signal irq_mask_reg      : std_logic_vector(7 downto 0);
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   signal irq_status        : std_logic_vector(7 downto 0);
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   signal irq               : std_logic;
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   signal irq_eth_rec       : std_logic;
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   signal irq_eth_send      : std_logic;
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   signal counter_reg       : std_logic_vector(31 downto 0);
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   signal ram_enable        : std_logic;
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   signal ram_byte_we       : std_logic_vector(3 downto 0);
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   signal ram_address       : std_logic_vector(31 downto 2);
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   signal ram_data_w        : std_logic_vector(31 downto 0);
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   signal ram_data_r        : std_logic_vector(31 downto 0);
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   signal cache_access      : std_logic;
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   signal cache_checking    : std_logic;
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   signal cache_miss        : std_logic;
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   signal cache_hit         : std_logic;
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begin  --architecture
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   write_enable <= '1' when cpu_byte_we /= "0000" else '0';
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   mem_busy <= eth_pause or mem_pause_in;
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   cache_hit <= cache_checking and not cache_miss;
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   cpu_pause <= (uart_write_busy and enable_uart and write_enable) or  --UART busy
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      cache_miss or                                                    --Cache wait
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      (cpu_address(28) and not cache_hit and mem_busy);                --DDR or flash
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   irq_status <= gpioA_in(31) & not gpioA_in(31) &
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                 irq_eth_send & irq_eth_rec &
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                 counter_reg(18) & not counter_reg(18) &
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                 not uart_write_busy & uart_data_avail;
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   irq <= '1' when (irq_status and irq_mask_reg) /= ZERO(7 downto 0) else '0';
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   gpio0_out(31 downto 29) <= gpio0_reg(31 downto 29);
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   gpio0_out(23 downto 0) <= gpio0_reg(23 downto 0);
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   enable_misc <= '1' when cpu_address(30 downto 28) = "010" else '0';
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   enable_uart <= '1' when enable_misc = '1' and cpu_address(7 downto 4) = "0000" else '0';
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   enable_uart_read <= enable_uart and not write_enable;
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   enable_uart_write <= enable_uart and write_enable;
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   enable_eth <= '1' when enable_misc = '1' and cpu_address(7 downto 4) = "0111" else '0';
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   cpu_address(1 downto 0) <= "00";
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   u1_cpu: mlite_cpu
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      generic map (memory_type => memory_type)
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      PORT MAP (
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         clk          => clk,
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         reset_in     => reset,
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         intr_in      => irq,
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         address_next => address_next,             --before rising_edge(clk)
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         byte_we_next => byte_we_next,
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         address      => cpu_address(31 downto 2), --after rising_edge(clk)
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         byte_we      => cpu_byte_we,
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         data_w       => cpu_data_w,
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         data_r       => cpu_data_r,
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         mem_pause    => cpu_pause);
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   opt_cache: if use_cache = '0' generate
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      cache_access <= '0';
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      cache_checking <= '0';
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      cache_miss <= '0';
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   end generate;
147
 
148
   opt_cache2: if use_cache = '1' generate
149
   --Control 4KB unified cache that uses the upper 4KB of the 8KB
150
   --internal RAM.  Only lowest 2MB of DDR is cached.
151
   u_cache: cache
152
      generic map (memory_type => memory_type)
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      PORT MAP (
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         clk            => clk,
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         reset          => reset,
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         address_next   => address_next,
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         byte_we_next   => byte_we_next,
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         cpu_address    => cpu_address(31 downto 2),
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         mem_busy       => mem_busy,
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         cache_access   => cache_access,    --access 4KB cache
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         cache_checking => cache_checking,  --checking if cache hit
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         cache_miss     => cache_miss);     --cache miss
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   end generate; --opt_cache2
165
 
166
   no_ddr_start <= not eth_pause and cache_checking;
167
   no_ddr_stop <= not eth_pause and cache_miss;
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   eth_pause_in <= mem_pause_in or (not eth_pause and cache_miss and not cache_checking);
169
 
170
   misc_proc: process(clk, reset, cpu_address, enable_misc,
171
      ram_data_r, data_read, data_read_uart, cpu_pause,
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      irq_mask_reg, irq_status, gpio0_reg, write_enable,
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      cache_checking,
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      gpioA_in, counter_reg, cpu_data_w)
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   begin
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      case cpu_address(30 downto 28) is
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      when "000" =>         --internal RAM
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         cpu_data_r <= ram_data_r;
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      when "001" =>         --external RAM
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         if cache_checking = '1' then
181
            cpu_data_r <= ram_data_r; --cache
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         else
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            cpu_data_r <= data_read; --DDR
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         end if;
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      when "010" =>         --misc
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         case cpu_address(6 downto 4) is
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         when "000" =>      --uart
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            cpu_data_r <= ZERO(31 downto 8) & data_read_uart;
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         when "001" =>      --irq_mask
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            cpu_data_r <= ZERO(31 downto 8) & irq_mask_reg;
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         when "010" =>      --irq_status
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            cpu_data_r <= ZERO(31 downto 8) & irq_status;
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         when "011" =>      --gpio0
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            cpu_data_r <= gpio0_reg;
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         when "101" =>      --gpioA
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            cpu_data_r <= gpioA_in;
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         when "110" =>      --counter
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            cpu_data_r <= counter_reg;
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         when others =>
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            cpu_data_r <= gpioA_in;
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         end case;
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      when "011" =>         --flash
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         cpu_data_r <= data_read;
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      when others =>
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         cpu_data_r <= ZERO;
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      end case;
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208
      if reset = '1' then
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         irq_mask_reg <= ZERO(7 downto 0);
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         gpio0_reg <= ZERO;
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         counter_reg <= ZERO;
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      elsif rising_edge(clk) then
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         if cpu_pause = '0' then
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            if enable_misc = '1' and write_enable = '1' then
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               if cpu_address(6 downto 4) = "001" then
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                  irq_mask_reg <= cpu_data_w(7 downto 0);
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               elsif cpu_address(6 downto 4) = "011" then
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                  gpio0_reg <= gpio0_reg or cpu_data_w;
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               elsif cpu_address(6 downto 4) = "100" then
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                  gpio0_reg <= gpio0_reg and not cpu_data_w;
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               end if;
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            end if;
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         end if;
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         counter_reg <= bv_inc(counter_reg);
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      end if;
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   end process;
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   ram_proc: process(cache_access, cache_miss,
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                     address_next, cpu_address,
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                     byte_we_next, cpu_data_w, data_read)
231
   begin
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      if cache_access = '1' then    --Check if cache hit or write through
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         ram_enable <= '1';
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         ram_byte_we <= byte_we_next;
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         ram_address(31 downto 2) <= ZERO(31 downto 16) &
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            "0001" & address_next(11 downto 2);
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         ram_data_w <= cpu_data_w;
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      elsif cache_miss = '1' then  --Update cache after cache miss
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         ram_enable <= '1';
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         ram_byte_we <= "1111";
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         ram_address(31 downto 2) <= ZERO(31 downto 16) &
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            "0001" & cpu_address(11 downto 2);
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         ram_data_w <= data_read;
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      else                         --Normal non-cache access
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         if address_next(30 downto 28) = "000" then
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            ram_enable <= '1';
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         else
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            ram_enable <= '0';
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         end if;
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         ram_byte_we <= byte_we_next;
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         ram_address(31 downto 2) <= address_next(31 downto 2);
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         ram_data_w <= cpu_data_w;
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      end if;
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   end process;
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   u2_ram: ram
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      generic map (memory_type => memory_type)
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      port map (
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         clk               => clk,
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         enable            => ram_enable,
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         write_byte_enable => ram_byte_we,
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         address           => ram_address,
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         data_write        => ram_data_w,
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         data_read         => ram_data_r);
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266
   u3_uart: uart
267
      generic map (log_file => log_file)
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      port map(
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         clk          => clk,
270
         reset        => reset,
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         enable_read  => enable_uart_read,
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         enable_write => enable_uart_write,
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         data_in      => cpu_data_w(7 downto 0),
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         data_out     => data_read_uart,
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         uart_read    => uart_read,
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         uart_write   => uart_write,
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         busy_write   => uart_write_busy,
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         data_avail   => uart_data_avail);
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   dma_gen: if ethernet = '0' generate
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      address <= cpu_address(31 downto 2);
282
      byte_we <= cpu_byte_we;
283
      data_write <= cpu_data_w;
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      eth_pause <= '0';
285
      gpio0_out(28 downto 24) <= ZERO(28 downto 24);
286
      irq_eth_rec <= '0';
287
      irq_eth_send <= '0';
288
   end generate;
289
 
290
   dma_gen2: if ethernet = '1' generate
291
   u4_eth: eth_dma
292
      port map(
293
         clk         => clk,
294
         reset       => reset,
295
         enable_eth  => gpio0_reg(24),
296
         select_eth  => enable_eth,
297
         rec_isr     => irq_eth_rec,
298
         send_isr    => irq_eth_send,
299
 
300
         address     => address,      --to DDR
301
         byte_we     => byte_we,
302
         data_write  => data_write,
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         data_read   => data_read,
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         pause_in    => eth_pause_in,
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306 346 rhoads
         mem_address => cpu_address(31 downto 2), --from CPU
307
         mem_byte_we => cpu_byte_we,
308
         data_w      => cpu_data_w,
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         pause_out   => eth_pause,
310
 
311
         E_RX_CLK    => gpioA_in(20),
312
         E_RX_DV     => gpioA_in(19),
313
         E_RXD       => gpioA_in(18 downto 15),
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         E_TX_CLK    => gpioA_in(14),
315
         E_TX_EN     => gpio0_out(28),
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         E_TXD       => gpio0_out(27 downto 24));
317
   end generate;
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319 48 rhoads
end; --architecture logic
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