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rhoads |
---------------------------------------------------------------------
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-- TITLE: Plamsa Interface (clock divider and interface to FPGA board)
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-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
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-- DATE CREATED: 9/15/07
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-- FILENAME: plasma_3e.vhd
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-- PROJECT: Plasma CPU core
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-- COPYRIGHT: Software placed into the public domain by the author.
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-- Software 'as is' without warranty. Author liable for nothing.
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-- DESCRIPTION:
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-- This entity divides the clock by two and interfaces to the
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-- Xilinx Spartan-3E XC3S200FT256-4 FPGA with DDR.
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---------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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--use work.mlite_pack.all;
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entity plasma_3e is
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port(CLK_50MHZ : in std_logic;
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RS232_DCE_RXD : in std_logic;
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RS232_DCE_TXD : out std_logic;
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SD_CK_P : out std_logic; --clock_positive
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SD_CK_N : out std_logic; --clock_negative
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SD_CKE : out std_logic; --clock_enable
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SD_BA : out std_logic_vector(1 downto 0); --bank_address
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SD_A : out std_logic_vector(12 downto 0); --address(row or col)
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SD_CS : out std_logic; --chip_select
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SD_RAS : out std_logic; --row_address_strobe
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SD_CAS : out std_logic; --column_address_strobe
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SD_WE : out std_logic; --write_enable
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SD_DQ : inout std_logic_vector(15 downto 0); --data
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SD_UDM : out std_logic; --upper_byte_enable
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SD_UDQS : inout std_logic; --upper_data_strobe
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SD_LDM : out std_logic; --low_byte_enable
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SD_LDQS : inout std_logic; --low_data_strobe
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LED : out std_logic_vector(7 downto 0);
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ROT_CENTER : in std_logic;
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ROT_A : in std_logic;
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ROT_B : in std_logic;
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BTN_EAST : in std_logic;
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BTN_NORTH : in std_logic;
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BTN_SOUTH : in std_logic;
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BTN_WEST : in std_logic;
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SW : in std_logic_vector(3 downto 0));
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end; --entity plasma_if
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architecture logic of plasma_3e is
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component plasma
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generic(memory_type : string := "XILINX_16X"; --"DUAL_PORT_" "ALTERA_LPM";
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log_file : string := "UNUSED");
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port(clk : in std_logic;
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reset : in std_logic;
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uart_write : out std_logic;
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uart_read : in std_logic;
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address : out std_logic_vector(31 downto 2);
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byte_we : out std_logic_vector(3 downto 0);
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data_write : out std_logic_vector(31 downto 0);
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data_read : in std_logic_vector(31 downto 0);
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mem_pause_in : in std_logic;
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gpio0_out : out std_logic_vector(31 downto 0);
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gpioA_in : in std_logic_vector(31 downto 0));
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end component; --plasma
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component ddr_ctrl
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port(clk : in std_logic;
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clk_2x : in std_logic;
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reset_in : in std_logic;
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address : in std_logic_vector(25 downto 2);
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byte_we : in std_logic_vector(3 downto 0);
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data_w : in std_logic_vector(31 downto 0);
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data_r : out std_logic_vector(31 downto 0);
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active : in std_logic;
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pause : out std_logic;
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SD_CK_P : out std_logic; --clock_positive
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SD_CK_N : out std_logic; --clock_negative
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SD_CKE : out std_logic; --clock_enable
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SD_BA : out std_logic_vector(1 downto 0); --bank_address
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SD_A : out std_logic_vector(12 downto 0); --address(row or col)
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SD_CS : out std_logic; --chip_select
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SD_RAS : out std_logic; --row_address_strobe
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SD_CAS : out std_logic; --column_address_strobe
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SD_WE : out std_logic; --write_enable
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SD_DQ : inout std_logic_vector(15 downto 0); --data
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SD_UDM : out std_logic; --upper_byte_enable
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SD_UDQS : inout std_logic; --upper_data_strobe
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SD_LDM : out std_logic; --low_byte_enable
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SD_LDQS : inout std_logic); --low_data_strobe
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end component; --ddr
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signal clk_reg : std_logic;
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signal address : std_logic_vector(31 downto 2);
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signal data_write : std_logic_vector(31 downto 0);
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signal data_read : std_logic_vector(31 downto 0);
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signal byte_we : std_logic_vector(3 downto 0);
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signal pause : std_logic;
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signal active : std_logic;
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signal reset : std_logic;
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signal gpio0_out : std_logic_vector(31 downto 0);
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signal gpio0_in : std_logic_vector(31 downto 0);
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begin --architecture
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--Divide 50 MHz clock by two
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clk_div: process(reset, CLK_50MHZ, clk_reg)
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begin
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if reset = '1' then
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clk_reg <= '0';
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elsif rising_edge(CLK_50MHZ) then
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clk_reg <= not clk_reg;
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end if;
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end process; --clk_div
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reset <= ROT_CENTER;
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LED <= gpio0_out(7 downto 0);
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gpio0_in(31 downto 10) <= (others => '0');
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gpio0_in(9 downto 0) <= ROT_A & ROT_B & BTN_EAST & BTN_NORTH &
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BTN_SOUTH & BTN_WEST & SW;
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active <= '1' when address(31 downto 28) = "0001" else '0';
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u1_plama: plasma
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generic map (memory_type => "XILINX_16X",
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log_file => "UNUSED")
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--generic map (memory_type => "DUAL_PORT",
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-- log_file => "output2.txt")
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PORT MAP (
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clk => clk_reg,
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reset => reset,
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uart_write => RS232_DCE_TXD,
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uart_read => RS232_DCE_RXD,
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address => address,
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byte_we => byte_we,
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data_write => data_write,
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data_read => data_read,
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mem_pause_in => pause,
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gpio0_out => gpio0_out,
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gpioA_in => gpio0_in);
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u2_ddr: ddr_ctrl
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port map (
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clk => clk_reg,
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clk_2x => CLK_50MHZ,
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reset_in => reset,
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address => address(25 downto 2),
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byte_we => byte_we,
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data_w => data_write,
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data_r => data_read,
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active => active,
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pause => pause,
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SD_CK_P => SD_CK_P, --clock_positive
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SD_CK_N => SD_CK_N, --clock_negative
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SD_CKE => SD_CKE, --clock_enable
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SD_BA => SD_BA, --bank_address
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SD_A => SD_A, --address(row or col)
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SD_CS => SD_CS, --chip_select
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SD_RAS => SD_RAS, --row_address_strobe
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SD_CAS => SD_CAS, --column_address_strobe
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SD_WE => SD_WE, --write_enable
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SD_DQ => SD_DQ, --data
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SD_UDM => SD_UDM, --upper_byte_enable
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SD_UDQS => SD_UDQS, --upper_data_strobe
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SD_LDM => SD_LDM, --low_byte_enable
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SD_LDQS => SD_LDQS); --low_data_strobe
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end; --architecture logic
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