URL https://opencores.org/ocsvn/plasma/plasma/trunk

Subversion Repositories plasma

[/] [plasma/] [trunk/] [vhdl/] [plasma_3e.vhd] - Blame information for rev 287

Go to most recent revision | Details | Compare with Previous | View Log


---------------------------------------------------------------------
-- TITLE: Plamsa Interface (clock divider and interface to FPGA board)
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 9/15/07
-- FILENAME: plasma_3e.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
--    Software 'as is' without warranty.  Author liable for nothing.
-- DESCRIPTION:
--    This entity divides the clock by two and interfaces to the 
--    Xilinx Spartan-3E XC3S200FT256-4 FPGA with DDR.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
--use work.mlite_pack.all;
 
entity plasma_3e is
   port(CLK_50MHZ  : in std_logic;
        RS232_DCE_RXD : in std_logic;
        RS232_DCE_TXD : out std_logic;
 
        SD_CK_P    : out std_logic;     --DDR SDRAM clock_positive
        SD_CK_N    : out std_logic;     --clock_negative
        SD_CKE     : out std_logic;     --clock_enable
 
        SD_BA      : out std_logic_vector(1 downto 0);  --bank_address
        SD_A       : out std_logic_vector(12 downto 0); --address(row or col)
        SD_CS      : out std_logic;     --chip_select
        SD_RAS     : out std_logic;     --row_address_strobe
        SD_CAS     : out std_logic;     --column_address_strobe
        SD_WE      : out std_logic;     --write_enable
 
        SD_DQ      : inout std_logic_vector(15 downto 0); --data
        SD_UDM     : out std_logic;     --upper_byte_enable
        SD_UDQS    : inout std_logic;   --upper_data_strobe
        SD_LDM     : out std_logic;     --low_byte_enable
        SD_LDQS    : inout std_logic;   --low_data_strobe
 
        E_MDC      : out std_logic;     --Ethernet PHY
        E_MDIO     : inout std_logic;   --management data in/out
        E_RX_CLK   : in std_logic;      --receive clock
        E_RX_DV    : in std_logic;      --data valid
        E_RXD      : in std_logic_vector(3 downto 0);
        E_TX_CLK   : in std_logic;      --transmit clock
        E_TX_EN    : out std_logic;     --data valid
        E_TXD      : out std_logic_vector(3 downto 0);
 
        SF_CE0     : out std_logic;     --NOR flash
        SF_OE      : out std_logic;
        SF_WE      : out std_logic;
        SF_BYTE    : out std_logic;
        SF_STS     : in std_logic;      --status
        SF_A       : out std_logic_vector(24 downto 0);
        SF_D       : inout std_logic_vector(15 downto 1);
        SPI_MISO   : inout std_logic;
 
        VGA_VSYNC  : out std_logic;     --VGA port
        VGA_HSYNC  : out std_logic;
        VGA_RED    : out std_logic;
        VGA_GREEN  : out std_logic;
        VGA_BLUE   : out std_logic;
 
        PS2_CLK    : in std_logic;      --Keyboard
        PS2_DATA   : in std_logic;
 
        LED        : out std_logic_vector(7 downto 0);
        ROT_CENTER : in std_logic;
        ROT_A      : in std_logic;
        ROT_B      : in std_logic;
        BTN_EAST   : in std_logic;
        BTN_NORTH  : in std_logic;
        BTN_SOUTH  : in std_logic;
        BTN_WEST   : in std_logic;
        SW         : in std_logic_vector(3 downto 0));
end; --entity plasma_if
 
 
architecture logic of plasma_3e is
 
   component plasma
      generic(memory_type : string := "XILINX_16X"; --"DUAL_PORT_" "ALTERA_LPM";
              log_file    : string := "UNUSED";
              ethernet    : std_logic := '0');
      port(clk          : in std_logic;
           reset        : in std_logic;
           uart_write   : out std_logic;
           uart_read    : in std_logic;
 
           address      : out std_logic_vector(31 downto 2);
           byte_we      : out std_logic_vector(3 downto 0);
           data_write   : out std_logic_vector(31 downto 0);
           data_read    : in std_logic_vector(31 downto 0);
           mem_pause_in : in std_logic;
 
           gpio0_out    : out std_logic_vector(31 downto 0);
           gpioA_in     : in std_logic_vector(31 downto 0));
   end component; --plasma
 
   component ddr_ctrl
      port(clk      : in std_logic;
           clk_2x   : in std_logic;
           reset_in : in std_logic;
 
           address  : in std_logic_vector(25 downto 2);
           byte_we  : in std_logic_vector(3 downto 0);
           data_w   : in std_logic_vector(31 downto 0);
           data_r   : out std_logic_vector(31 downto 0);
           active   : in std_logic;
           pause    : out std_logic;
 
           SD_CK_P  : out std_logic;     --clock_positive
           SD_CK_N  : out std_logic;     --clock_negative
           SD_CKE   : out std_logic;     --clock_enable
 
           SD_BA    : out std_logic_vector(1 downto 0);  --bank_address
           SD_A     : out std_logic_vector(12 downto 0); --address(row or col)
           SD_CS    : out std_logic;     --chip_select
           SD_RAS   : out std_logic;     --row_address_strobe
           SD_CAS   : out std_logic;     --column_address_strobe
           SD_WE    : out std_logic;     --write_enable
 
           SD_DQ    : inout std_logic_vector(15 downto 0); --data
           SD_UDM   : out std_logic;     --upper_byte_enable
           SD_UDQS  : inout std_logic;   --upper_data_strobe
           SD_LDM   : out std_logic;     --low_byte_enable
           SD_LDQS  : inout std_logic);  --low_data_strobe
   end component; --ddr
 
   signal clk_reg      : std_logic;
   signal address      : std_logic_vector(31 downto 2);
   signal data_write   : std_logic_vector(31 downto 0);
   signal data_read    : std_logic_vector(31 downto 0);
   signal data_r_ddr   : std_logic_vector(31 downto 0);
   signal byte_we      : std_logic_vector(3 downto 0);
   signal write_enable : std_logic;
   signal pause_ddr    : std_logic;
   signal pause        : std_logic;
   signal ddr_active   : std_logic;
   signal flash_active : std_logic;
   signal flash_cnt    : std_logic_vector(1 downto 0);
   signal flash_we     : std_logic;
   signal reset        : std_logic;
   signal gpio0_out    : std_logic_vector(31 downto 0);
   signal gpio0_in     : std_logic_vector(31 downto 0);
 
begin  --architecture
   --Divide 50 MHz clock by two
   clk_div: process(reset, CLK_50MHZ, clk_reg)
   begin
      if reset = '1' then
         clk_reg <= '0';
      elsif rising_edge(CLK_50MHZ) then
         clk_reg <= not clk_reg;
      end if;
   end process; --clk_div
 
   reset <= ROT_CENTER;
   E_TX_EN   <= gpio0_out(28);  --Ethernet
   E_TXD     <= gpio0_out(27 downto 24);
   E_MDC     <= gpio0_out(23);
   E_MDIO    <= gpio0_out(21) when gpio0_out(22) = '1' else 'Z';
   VGA_VSYNC <= gpio0_out(20);
   VGA_HSYNC <= gpio0_out(19);
   VGA_RED   <= gpio0_out(18);
   VGA_GREEN <= gpio0_out(17);
   VGA_BLUE  <= gpio0_out(16);
   LED <= gpio0_out(7 downto 0);
   gpio0_in(31 downto 21) <= (others => '0');
   gpio0_in(20 downto 13) <= E_RX_CLK & E_RX_DV & E_RXD & E_TX_CLK & E_MDIO;
   gpio0_in(12 downto 10) <= SF_STS & PS2_CLK & PS2_DATA;
   gpio0_in(9 downto 0) <= ROT_A & ROT_B & BTN_EAST & BTN_NORTH &
                           BTN_SOUTH & BTN_WEST & SW;
   ddr_active <= '1' when address(31 downto 28) = "0001" else '0';
   flash_active <= '1' when address(31 downto 28) = "0011" else '0';
   write_enable <= '1' when byte_we /= "0000" else '0';
 
   u1_plama: plasma
      generic map (memory_type => "XILINX_16X",
                   log_file    => "UNUSED",
                   ethernet    => '1')
      --generic map (memory_type => "DUAL_PORT_",
      --             log_file    => "output2.txt",
      --             ethernet    => '1')
      PORT MAP (
         clk          => clk_reg,
         reset        => reset,
         uart_write   => RS232_DCE_TXD,
         uart_read    => RS232_DCE_RXD,
 
         address      => address,
         byte_we      => byte_we,
         data_write   => data_write,
         data_read    => data_read,
         mem_pause_in => pause,
 
         gpio0_out    => gpio0_out,
         gpioA_in     => gpio0_in);
 
   u2_ddr: ddr_ctrl
      port map (
         clk      => clk_reg,
         clk_2x   => CLK_50MHZ,
         reset_in => reset,
 
         address  => address(25 downto 2),
         byte_we  => byte_we,
         data_w   => data_write,
         data_r   => data_r_ddr,
         active   => ddr_active,
         pause    => pause_ddr,
 
         SD_CK_P  => SD_CK_P,    --clock_positive
         SD_CK_N  => SD_CK_N,    --clock_negative
         SD_CKE   => SD_CKE,     --clock_enable
 
         SD_BA    => SD_BA,      --bank_address
         SD_A     => SD_A,       --address(row or col)
         SD_CS    => SD_CS,      --chip_select
         SD_RAS   => SD_RAS,     --row_address_strobe
         SD_CAS   => SD_CAS,     --column_address_strobe
         SD_WE    => SD_WE,      --write_enable
 
         SD_DQ    => SD_DQ,      --data
         SD_UDM   => SD_UDM,     --upper_byte_enable
         SD_UDQS  => SD_UDQS,    --upper_data_strobe
         SD_LDM   => SD_LDM,     --low_byte_enable
         SD_LDQS  => SD_LDQS);   --low_data_strobe
 
   --Flash control (only lower 16-bit data lines connected)
   flash_ctrl: process(reset, clk_reg, flash_active, write_enable,
                       flash_cnt, pause_ddr)
   begin
      if reset = '1' then
         flash_cnt <= "00";
         flash_we <= '1';
      elsif rising_edge(clk_reg) then
         if flash_active = '0' then
            flash_cnt <= "00";
            flash_we <= '1';
         else
            if write_enable = '1' and flash_cnt(1) = '0' then
               flash_we <= '0';
            else
               flash_we <= '1';
            end if;
            if flash_cnt /= "11" then
               flash_cnt <= flash_cnt + 1;
            end if;
         end if;
      end if;  --rising_edge(clk_reg)
      if pause_ddr = '1' or (flash_active = '1' and flash_cnt /= "11") then
         pause <= '1';
      else
         pause <= '0';
      end if;
   end process; --flash_ctrl
 
   SF_CE0  <= not flash_active;
   SF_OE   <= write_enable or not flash_active;
   SF_WE   <= flash_we;
   SF_BYTE <= '1';  --16-bit access
   SF_A    <= address(25 downto 2) & '0';
   SF_D    <= data_write(15 downto 1) when
              flash_active = '1' and write_enable = '1'
              else "ZZZZZZZZZZZZZZZ";
   SPI_MISO <= data_write(0) when
              flash_active = '1' and write_enable = '1'
              else 'Z';
   data_read(31 downto 16) <= data_r_ddr(31 downto 16);
   data_read(15 downto 0) <= data_r_ddr(15 downto 0) when flash_active = '0'
                             else SF_D & SPI_MISO;
 
end; --architecture logic
 

Line No.	Rev	Author	Line
1	259	rhoads	`---------------------------------------------------------------------`
2			`-- TITLE: Plamsa Interface (clock divider and interface to FPGA board)`
3			`-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)`
4			`-- DATE CREATED: 9/15/07`
5			`-- FILENAME: plasma_3e.vhd`
6			`-- PROJECT: Plasma CPU core`
7			`-- COPYRIGHT: Software placed into the public domain by the author.`
8			`-- Software 'as is' without warranty. Author liable for nothing.`
9			`-- DESCRIPTION:`
10			`-- This entity divides the clock by two and interfaces to the`
11			`-- Xilinx Spartan-3E XC3S200FT256-4 FPGA with DDR.`
12			`---------------------------------------------------------------------`
13			`library ieee;`
14			`use ieee.std_logic_1164.all;`
15	287	rhoads	`use ieee.std_logic_unsigned.all;`
16			`use ieee.std_logic_arith.all;`
17	259	rhoads	`--use work.mlite_pack.all;`
18
19			`entity plasma_3e is`
20			`port(CLK_50MHZ : in std_logic;`
21			`RS232_DCE_RXD : in std_logic;`
22			`RS232_DCE_TXD : out std_logic;`
23
24	287	rhoads	`SD_CK_P : out std_logic; --DDR SDRAM clock_positive`
25	259	rhoads	`SD_CK_N : out std_logic; --clock_negative`
26			`SD_CKE : out std_logic; --clock_enable`
27
28			`SD_BA : out std_logic_vector(1 downto 0); --bank_address`
29			`SD_A : out std_logic_vector(12 downto 0); --address(row or col)`
30			`SD_CS : out std_logic; --chip_select`
31			`SD_RAS : out std_logic; --row_address_strobe`
32			`SD_CAS : out std_logic; --column_address_strobe`
33			`SD_WE : out std_logic; --write_enable`
34
35			`SD_DQ : inout std_logic_vector(15 downto 0); --data`
36			`SD_UDM : out std_logic; --upper_byte_enable`
37			`SD_UDQS : inout std_logic; --upper_data_strobe`
38			`SD_LDM : out std_logic; --low_byte_enable`
39			`SD_LDQS : inout std_logic; --low_data_strobe`
40
41	287	rhoads	`E_MDC : out std_logic; --Ethernet PHY`
42			`E_MDIO : inout std_logic; --management data in/out`
43			`E_RX_CLK : in std_logic; --receive clock`
44			`E_RX_DV : in std_logic; --data valid`
45			`E_RXD : in std_logic_vector(3 downto 0);`
46			`E_TX_CLK : in std_logic; --transmit clock`
47			`E_TX_EN : out std_logic; --data valid`
48			`E_TXD : out std_logic_vector(3 downto 0);`
49
50			`SF_CE0 : out std_logic; --NOR flash`
51			`SF_OE : out std_logic;`
52			`SF_WE : out std_logic;`
53			`SF_BYTE : out std_logic;`
54			`SF_STS : in std_logic; --status`
55			`SF_A : out std_logic_vector(24 downto 0);`
56			`SF_D : inout std_logic_vector(15 downto 1);`
57			`SPI_MISO : inout std_logic;`
58
59			`VGA_VSYNC : out std_logic; --VGA port`
60			`VGA_HSYNC : out std_logic;`
61			`VGA_RED : out std_logic;`
62			`VGA_GREEN : out std_logic;`
63			`VGA_BLUE : out std_logic;`
64
65			`PS2_CLK : in std_logic; --Keyboard`
66			`PS2_DATA : in std_logic;`
67
68	259	rhoads	`LED : out std_logic_vector(7 downto 0);`
69			`ROT_CENTER : in std_logic;`
70			`ROT_A : in std_logic;`
71			`ROT_B : in std_logic;`
72			`BTN_EAST : in std_logic;`
73			`BTN_NORTH : in std_logic;`
74			`BTN_SOUTH : in std_logic;`
75			`BTN_WEST : in std_logic;`
76			`SW : in std_logic_vector(3 downto 0));`
77			`end; --entity plasma_if`
78
79
80			`architecture logic of plasma_3e is`
81
82			`component plasma`
83			`generic(memory_type : string := "XILINX_16X"; --"DUAL_PORT_" "ALTERA_LPM";`
84	287	rhoads	`log_file : string := "UNUSED";`
85			`ethernet : std_logic := '0');`
86	259	rhoads	`port(clk : in std_logic;`
87			`reset : in std_logic;`
88			`uart_write : out std_logic;`
89			`uart_read : in std_logic;`
90
91			`address : out std_logic_vector(31 downto 2);`
92			`byte_we : out std_logic_vector(3 downto 0);`
93			`data_write : out std_logic_vector(31 downto 0);`
94			`data_read : in std_logic_vector(31 downto 0);`
95			`mem_pause_in : in std_logic;`
96
97			`gpio0_out : out std_logic_vector(31 downto 0);`
98			`gpioA_in : in std_logic_vector(31 downto 0));`
99			`end component; --plasma`
100
101			`component ddr_ctrl`
102			`port(clk : in std_logic;`
103			`clk_2x : in std_logic;`
104			`reset_in : in std_logic;`
105
106			`address : in std_logic_vector(25 downto 2);`
107			`byte_we : in std_logic_vector(3 downto 0);`
108			`data_w : in std_logic_vector(31 downto 0);`
109			`data_r : out std_logic_vector(31 downto 0);`
110			`active : in std_logic;`
111			`pause : out std_logic;`
112
113			`SD_CK_P : out std_logic; --clock_positive`
114			`SD_CK_N : out std_logic; --clock_negative`
115			`SD_CKE : out std_logic; --clock_enable`
116
117			`SD_BA : out std_logic_vector(1 downto 0); --bank_address`
118			`SD_A : out std_logic_vector(12 downto 0); --address(row or col)`
119			`SD_CS : out std_logic; --chip_select`
120			`SD_RAS : out std_logic; --row_address_strobe`
121			`SD_CAS : out std_logic; --column_address_strobe`
122			`SD_WE : out std_logic; --write_enable`
123
124			`SD_DQ : inout std_logic_vector(15 downto 0); --data`
125			`SD_UDM : out std_logic; --upper_byte_enable`
126			`SD_UDQS : inout std_logic; --upper_data_strobe`
127			`SD_LDM : out std_logic; --low_byte_enable`
128			`SD_LDQS : inout std_logic); --low_data_strobe`
129			`end component; --ddr`
130
131			`signal clk_reg : std_logic;`
132			`signal address : std_logic_vector(31 downto 2);`
133			`signal data_write : std_logic_vector(31 downto 0);`
134			`signal data_read : std_logic_vector(31 downto 0);`
135	287	rhoads	`signal data_r_ddr : std_logic_vector(31 downto 0);`
136	259	rhoads	`signal byte_we : std_logic_vector(3 downto 0);`
137	287	rhoads	`signal write_enable : std_logic;`
138			`signal pause_ddr : std_logic;`
139	259	rhoads	`signal pause : std_logic;`
140	287	rhoads	`signal ddr_active : std_logic;`
141			`signal flash_active : std_logic;`
142			`signal flash_cnt : std_logic_vector(1 downto 0);`
143			`signal flash_we : std_logic;`
144	259	rhoads	`signal reset : std_logic;`
145			`signal gpio0_out : std_logic_vector(31 downto 0);`
146			`signal gpio0_in : std_logic_vector(31 downto 0);`
147
148			`begin --architecture`
149			`--Divide 50 MHz clock by two`
150			`clk_div: process(reset, CLK_50MHZ, clk_reg)`
151			`begin`
152			`if reset = '1' then`
153			`clk_reg <= '0';`
154			`elsif rising_edge(CLK_50MHZ) then`
155			`clk_reg <= not clk_reg;`
156			`end if;`
157			`end process; --clk_div`
158
159			`reset <= ROT_CENTER;`
160	287	rhoads	`E_TX_EN <= gpio0_out(28); --Ethernet`
161			`E_TXD <= gpio0_out(27 downto 24);`
162			`E_MDC <= gpio0_out(23);`
163			`E_MDIO <= gpio0_out(21) when gpio0_out(22) = '1' else 'Z';`
164			`VGA_VSYNC <= gpio0_out(20);`
165			`VGA_HSYNC <= gpio0_out(19);`
166			`VGA_RED <= gpio0_out(18);`
167			`VGA_GREEN <= gpio0_out(17);`
168			`VGA_BLUE <= gpio0_out(16);`
169	259	rhoads	`LED <= gpio0_out(7 downto 0);`
170	287	rhoads	`gpio0_in(31 downto 21) <= (others => '0');`
171			`gpio0_in(20 downto 13) <= E_RX_CLK & E_RX_DV & E_RXD & E_TX_CLK & E_MDIO;`
172			`gpio0_in(12 downto 10) <= SF_STS & PS2_CLK & PS2_DATA;`
173	259	rhoads	`gpio0_in(9 downto 0) <= ROT_A & ROT_B & BTN_EAST & BTN_NORTH &`
174			`BTN_SOUTH & BTN_WEST & SW;`
175	287	rhoads	`ddr_active <= '1' when address(31 downto 28) = "0001" else '0';`
176			`flash_active <= '1' when address(31 downto 28) = "0011" else '0';`
177			`write_enable <= '1' when byte_we /= "0000" else '0';`
178	259	rhoads
179			`u1_plama: plasma`
180			`generic map (memory_type => "XILINX_16X",`
181	287	rhoads	`log_file => "UNUSED",`
182			`ethernet => '1')`
183			`--generic map (memory_type => "DUAL_PORT_",`
184			`-- log_file => "output2.txt",`
185			`-- ethernet => '1')`
186	259	rhoads	`PORT MAP (`
187			`clk => clk_reg,`
188			`reset => reset,`
189			`uart_write => RS232_DCE_TXD,`
190			`uart_read => RS232_DCE_RXD,`
191
192			`address => address,`
193			`byte_we => byte_we,`
194			`data_write => data_write,`
195			`data_read => data_read,`
196			`mem_pause_in => pause,`
197
198			`gpio0_out => gpio0_out,`
199			`gpioA_in => gpio0_in);`
200
201			`u2_ddr: ddr_ctrl`
202			`port map (`
203			`clk => clk_reg,`
204			`clk_2x => CLK_50MHZ,`
205			`reset_in => reset,`
206
207			`address => address(25 downto 2),`
208			`byte_we => byte_we,`
209			`data_w => data_write,`
210	287	rhoads	`data_r => data_r_ddr,`
211			`active => ddr_active,`
212			`pause => pause_ddr,`
213	259	rhoads
214			`SD_CK_P => SD_CK_P, --clock_positive`
215			`SD_CK_N => SD_CK_N, --clock_negative`
216			`SD_CKE => SD_CKE, --clock_enable`
217
218			`SD_BA => SD_BA, --bank_address`
219			`SD_A => SD_A, --address(row or col)`
220			`SD_CS => SD_CS, --chip_select`
221			`SD_RAS => SD_RAS, --row_address_strobe`
222			`SD_CAS => SD_CAS, --column_address_strobe`
223			`SD_WE => SD_WE, --write_enable`
224
225			`SD_DQ => SD_DQ, --data`
226			`SD_UDM => SD_UDM, --upper_byte_enable`
227			`SD_UDQS => SD_UDQS, --upper_data_strobe`
228			`SD_LDM => SD_LDM, --low_byte_enable`
229			`SD_LDQS => SD_LDQS); --low_data_strobe`
230	287	rhoads
231			`--Flash control (only lower 16-bit data lines connected)`
232			`flash_ctrl: process(reset, clk_reg, flash_active, write_enable,`
233			`flash_cnt, pause_ddr)`
234			`begin`
235			`if reset = '1' then`
236			`flash_cnt <= "00";`
237			`flash_we <= '1';`
238			`elsif rising_edge(clk_reg) then`
239			`if flash_active = '0' then`
240			`flash_cnt <= "00";`
241			`flash_we <= '1';`
242			`else`
243			`if write_enable = '1' and flash_cnt(1) = '0' then`
244			`flash_we <= '0';`
245			`else`
246			`flash_we <= '1';`
247			`end if;`
248			`if flash_cnt /= "11" then`
249			`flash_cnt <= flash_cnt + 1;`
250			`end if;`
251			`end if;`
252			`end if; --rising_edge(clk_reg)`
253			`if pause_ddr = '1' or (flash_active = '1' and flash_cnt /= "11") then`
254			`pause <= '1';`
255			`else`
256			`pause <= '0';`
257			`end if;`
258			`end process; --flash_ctrl`
259
260			`SF_CE0 <= not flash_active;`
261			`SF_OE <= write_enable or not flash_active;`
262			`SF_WE <= flash_we;`
263			`SF_BYTE <= '1'; --16-bit access`
264			`SF_A <= address(25 downto 2) & '0';`
265			`SF_D <= data_write(15 downto 1) when`
266			`flash_active = '1' and write_enable = '1'`
267			`else "ZZZZZZZZZZZZZZZ";`
268			`SPI_MISO <= data_write(0) when`
269			`flash_active = '1' and write_enable = '1'`
270			`else 'Z';`
271			`data_read(31 downto 16) <= data_r_ddr(31 downto 16);`
272			`data_read(15 downto 0) <= data_r_ddr(15 downto 0) when flash_active = '0'`
273			`else SF_D & SPI_MISO;`
274	259	rhoads
275			`end; --architecture logic`
276

Browse

Tools

Subversion Repositories plasma

[/] [plasma/] [trunk/] [vhdl/] [plasma_3e.vhd] - Blame information for rev 287