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[/] [plasma/] [trunk/] [vhdl/] [plasma_3e.vhd] - Blame information for rev 406

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---------------------------------------------------------------------
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-- TITLE: Plamsa Interface (clock divider and interface to FPGA board)
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-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
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-- DATE CREATED: 9/15/07
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-- FILENAME: plasma_3e.vhd
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-- PROJECT: Plasma CPU core
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-- COPYRIGHT: Software placed into the public domain by the author.
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--    Software 'as is' without warranty.  Author liable for nothing.
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-- DESCRIPTION:
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--    This entity divides the clock by two and interfaces to the 
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--    Xilinx Spartan-3E XC3S200FT256-4 FPGA with DDR.
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---------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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--use work.mlite_pack.all;
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entity plasma_3e is
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   port(CLK_50MHZ  : in std_logic;
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        RS232_DCE_RXD : in std_logic;
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        RS232_DCE_TXD : out std_logic;
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        SD_CK_P    : out std_logic;     --DDR SDRAM clock_positive
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        SD_CK_N    : out std_logic;     --clock_negative
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        SD_CKE     : out std_logic;     --clock_enable
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        SD_BA      : out std_logic_vector(1 downto 0);  --bank_address
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        SD_A       : out std_logic_vector(12 downto 0); --address(row or col)
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        SD_CS      : out std_logic;     --chip_select
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        SD_RAS     : out std_logic;     --row_address_strobe
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        SD_CAS     : out std_logic;     --column_address_strobe
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        SD_WE      : out std_logic;     --write_enable
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        SD_DQ      : inout std_logic_vector(15 downto 0); --data
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        SD_UDM     : out std_logic;     --upper_byte_enable
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        SD_UDQS    : inout std_logic;   --upper_data_strobe
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        SD_LDM     : out std_logic;     --low_byte_enable
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        SD_LDQS    : inout std_logic;   --low_data_strobe
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        E_MDC      : out std_logic;     --Ethernet PHY
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        E_MDIO     : inout std_logic;   --management data in/out
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        E_RX_CLK   : in std_logic;      --receive clock
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        E_RX_DV    : in std_logic;      --data valid
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        E_RXD      : in std_logic_vector(3 downto 0);
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        E_TX_CLK   : in std_logic;      --transmit clock
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        E_TX_EN    : out std_logic;     --data valid
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        E_TXD      : out std_logic_vector(3 downto 0);
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        SF_CE0     : out std_logic;     --NOR flash
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        SF_OE      : out std_logic;
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        SF_WE      : out std_logic;
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        SF_BYTE    : out std_logic;
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        SF_STS     : in std_logic;      --status
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        SF_A       : out std_logic_vector(24 downto 0);
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        SF_D       : inout std_logic_vector(15 downto 1);
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        SPI_MISO   : inout std_logic;
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        VGA_VSYNC  : out std_logic;     --VGA port
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        VGA_HSYNC  : out std_logic;
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        VGA_RED    : out std_logic;
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        VGA_GREEN  : out std_logic;
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        VGA_BLUE   : out std_logic;
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        PS2_CLK    : in std_logic;      --Keyboard
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        PS2_DATA   : in std_logic;
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        LED        : out std_logic_vector(7 downto 0);
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        ROT_CENTER : in std_logic;
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        ROT_A      : in std_logic;
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        ROT_B      : in std_logic;
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        BTN_EAST   : in std_logic;
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        BTN_NORTH  : in std_logic;
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        BTN_SOUTH  : in std_logic;
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        BTN_WEST   : in std_logic;
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        SW         : in std_logic_vector(3 downto 0));
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end; --entity plasma_if
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architecture logic of plasma_3e is
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   component plasma
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      generic(memory_type : string := "XILINX_16X"; --"DUAL_PORT_" "ALTERA_LPM";
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              log_file    : string := "UNUSED";
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              ethernet    : std_logic := '0';
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              use_cache   : std_logic := '0');
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      port(clk          : in std_logic;
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           reset        : in std_logic;
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           uart_write   : out std_logic;
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           uart_read    : in std_logic;
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           address      : out std_logic_vector(31 downto 2);
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           byte_we      : out std_logic_vector(3 downto 0);
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           data_write   : out std_logic_vector(31 downto 0);
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           data_read    : in std_logic_vector(31 downto 0);
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           mem_pause_in : in std_logic;
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           no_ddr_start : out std_logic;
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           no_ddr_stop  : out std_logic;
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           gpio0_out    : out std_logic_vector(31 downto 0);
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           gpioA_in     : in std_logic_vector(31 downto 0));
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   end component; --plasma
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   component ddr_ctrl
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      port(clk      : in std_logic;
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           clk_2x   : in std_logic;
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           reset_in : in std_logic;
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           address  : in std_logic_vector(25 downto 2);
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           byte_we  : in std_logic_vector(3 downto 0);
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           data_w   : in std_logic_vector(31 downto 0);
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           data_r   : out std_logic_vector(31 downto 0);
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           active   : in std_logic;
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           no_start : in std_logic;
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           no_stop  : in std_logic;
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           pause    : out std_logic;
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           SD_CK_P  : out std_logic;     --clock_positive
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           SD_CK_N  : out std_logic;     --clock_negative
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           SD_CKE   : out std_logic;     --clock_enable
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           SD_BA    : out std_logic_vector(1 downto 0);  --bank_address
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           SD_A     : out std_logic_vector(12 downto 0); --address(row or col)
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           SD_CS    : out std_logic;     --chip_select
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           SD_RAS   : out std_logic;     --row_address_strobe
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           SD_CAS   : out std_logic;     --column_address_strobe
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           SD_WE    : out std_logic;     --write_enable
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129
           SD_DQ    : inout std_logic_vector(15 downto 0); --data
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           SD_UDM   : out std_logic;     --upper_byte_enable
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           SD_UDQS  : inout std_logic;   --upper_data_strobe
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           SD_LDM   : out std_logic;     --low_byte_enable
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           SD_LDQS  : inout std_logic);  --low_data_strobe
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   end component; --ddr
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   signal clk_reg      : std_logic;
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   signal address      : std_logic_vector(31 downto 2);
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   signal data_write   : std_logic_vector(31 downto 0);
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   signal data_read    : std_logic_vector(31 downto 0);
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   signal data_r_ddr   : std_logic_vector(31 downto 0);
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   signal byte_we      : std_logic_vector(3 downto 0);
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   signal write_enable : std_logic;
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   signal pause_ddr    : std_logic;
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   signal pause        : std_logic;
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   signal no_ddr_start : std_logic;
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   signal no_ddr_stop  : std_logic;
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   signal ddr_active   : std_logic;
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   signal flash_active : std_logic;
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   signal flash_cnt    : std_logic_vector(1 downto 0);
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   signal flash_we     : std_logic;
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   signal reset        : std_logic;
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   signal gpio0_out    : std_logic_vector(31 downto 0);
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   signal gpio0_in     : std_logic_vector(31 downto 0);
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155
begin  --architecture
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   --Divide 50 MHz clock by two
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   clk_div: process(reset, CLK_50MHZ, clk_reg)
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   begin
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      if reset = '1' then
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         clk_reg <= '0';
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      elsif rising_edge(CLK_50MHZ) then
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         clk_reg <= not clk_reg;
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      end if;
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   end process; --clk_div
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   reset <= ROT_CENTER;
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   E_TX_EN   <= gpio0_out(28);  --Ethernet
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   E_TXD     <= gpio0_out(27 downto 24);
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   E_MDC     <= gpio0_out(23);
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   E_MDIO    <= gpio0_out(21) when gpio0_out(22) = '1' else 'Z';
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   VGA_VSYNC <= gpio0_out(20);
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   VGA_HSYNC <= gpio0_out(19);
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   VGA_RED   <= gpio0_out(18);
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   VGA_GREEN <= gpio0_out(17);
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   VGA_BLUE  <= gpio0_out(16);
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   LED <= gpio0_out(7 downto 0);
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   gpio0_in(31 downto 21) <= (others => '0');
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   gpio0_in(20 downto 13) <= E_RX_CLK & E_RX_DV & E_RXD & E_TX_CLK & E_MDIO;
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   gpio0_in(12 downto 10) <= SF_STS & PS2_CLK & PS2_DATA;
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   gpio0_in(9 downto 0) <= ROT_A & ROT_B & BTN_EAST & BTN_NORTH &
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                           BTN_SOUTH & BTN_WEST & SW;
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   ddr_active <= '1' when address(31 downto 28) = "0001" else '0';
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   flash_active <= '1' when address(31 downto 28) = "0011" else '0';
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   write_enable <= '1' when byte_we /= "0000" else '0';
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   u1_plama: plasma
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      generic map (memory_type => "XILINX_16X",
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                   log_file    => "UNUSED",
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                   ethernet    => '1',
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                   use_cache   => '1')
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      --generic map (memory_type => "DUAL_PORT_",
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      --             log_file    => "output2.txt",
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      --             ethernet    => '1')
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      PORT MAP (
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         clk          => clk_reg,
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         reset        => reset,
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         uart_write   => RS232_DCE_TXD,
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         uart_read    => RS232_DCE_RXD,
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         address      => address,
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         byte_we      => byte_we,
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         data_write   => data_write,
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         data_read    => data_read,
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         mem_pause_in => pause,
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         no_ddr_start => no_ddr_start,
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         no_ddr_stop  => no_ddr_stop,
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         gpio0_out    => gpio0_out,
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         gpioA_in     => gpio0_in);
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   u2_ddr: ddr_ctrl
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      port map (
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         clk      => clk_reg,
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         clk_2x   => CLK_50MHZ,
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         reset_in => reset,
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         address  => address(25 downto 2),
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         byte_we  => byte_we,
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         data_w   => data_write,
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         data_r   => data_r_ddr,
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         active   => ddr_active,
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         no_start => no_ddr_start,
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         no_stop  => no_ddr_stop,
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         pause    => pause_ddr,
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         SD_CK_P  => SD_CK_P,    --clock_positive
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         SD_CK_N  => SD_CK_N,    --clock_negative
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         SD_CKE   => SD_CKE,     --clock_enable
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         SD_BA    => SD_BA,      --bank_address
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         SD_A     => SD_A,       --address(row or col)
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         SD_CS    => SD_CS,      --chip_select
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         SD_RAS   => SD_RAS,     --row_address_strobe
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         SD_CAS   => SD_CAS,     --column_address_strobe
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         SD_WE    => SD_WE,      --write_enable
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         SD_DQ    => SD_DQ,      --data
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         SD_UDM   => SD_UDM,     --upper_byte_enable
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         SD_UDQS  => SD_UDQS,    --upper_data_strobe
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         SD_LDM   => SD_LDM,     --low_byte_enable
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         SD_LDQS  => SD_LDQS);   --low_data_strobe
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   --Flash control (only lower 16-bit data lines connected)
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   flash_ctrl: process(reset, clk_reg, flash_active, write_enable,
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                       flash_cnt, pause_ddr)
246
   begin
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      if reset = '1' then
248
         flash_cnt <= "00";
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         flash_we <= '1';
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      elsif rising_edge(clk_reg) then
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         if flash_active = '0' then
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            flash_cnt <= "00";
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            flash_we <= '1';
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         else
255
            if write_enable = '1' and flash_cnt(1) = '0' then
256
               flash_we <= '0';
257
            else
258
               flash_we <= '1';
259
            end if;
260
            if flash_cnt /= "11" then
261
               flash_cnt <= flash_cnt + 1;
262
            end if;
263
         end if;
264
      end if;  --rising_edge(clk_reg)
265
      if pause_ddr = '1' or (flash_active = '1' and flash_cnt /= "11") then
266
         pause <= '1';
267
      else
268
         pause <= '0';
269
      end if;
270
   end process; --flash_ctrl
271
 
272
   SF_CE0  <= not flash_active;
273
   SF_OE   <= write_enable or not flash_active;
274
   SF_WE   <= flash_we;
275
   SF_BYTE <= '1';  --16-bit access
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   SF_A    <= address(25 downto 2) & '0' when flash_active = '1' else
277
              "0000000000000000000000000";
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   SF_D    <= data_write(15 downto 1) when
279
              flash_active = '1' and write_enable = '1'
280
              else "ZZZZZZZZZZZZZZZ";
281
   SPI_MISO <= data_write(0) when
282
              flash_active = '1' and write_enable = '1'
283
              else 'Z';
284
   data_read(31 downto 16) <= data_r_ddr(31 downto 16);
285
   data_read(15 downto 0) <= data_r_ddr(15 downto 0) when flash_active = '0'
286
                             else SF_D & SPI_MISO;
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288
end; --architecture logic
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