| 1 |
238 |
rhoads |
NET "clk_in" TNM_NET = "clk_in";
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| 2 |
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TIMESPEC "TS_clk_in" = PERIOD "clk_in" 20 ns HIGH 50 %;
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| 3 |
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#NET "clk_reg1" TNM_NET = "clk_reg1";
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| 4 |
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#TIMESPEC "TS_clk_reg1" = PERIOD "clk_reg1" 40 ns HIGH 50 %;
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| 5 |
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NET "clk_reg1" TNM_NET = "clk_reg1";
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| 6 |
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TIMESPEC "TS_clk_reg1" = PERIOD "clk_reg1" 39.9 ns HIGH 50 %;
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| 7 |
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#PACE: Start of Constraints generated by PACE
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| 8 |
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#PACE: Start of PACE I/O Pin Assignments
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| 9 |
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NET "clk_in" LOC = "T9";
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| 10 |
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NET "gpio0_out<0>" LOC = "K12";
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| 11 |
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NET "gpio0_out<10>" LOC = "N15";
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| 12 |
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NET "gpio0_out<11>" LOC = "P15";
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| 13 |
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NET "gpio0_out<12>" LOC = "R16";
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| 14 |
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NET "gpio0_out<13>" LOC = "F13";
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| 15 |
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NET "gpio0_out<14>" LOC = "N16";
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| 16 |
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NET "gpio0_out<15>" LOC = "P16";
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| 17 |
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NET "gpio0_out<16>" LOC = "E13";
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| 18 |
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NET "gpio0_out<17>" LOC = "F14";
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| 19 |
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NET "gpio0_out<18>" LOC = "G14";
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| 20 |
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NET "gpio0_out<19>" LOC = "D14";
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| 21 |
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NET "gpio0_out<1>" LOC = "P14";
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| 22 |
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NET "gpio0_out<24>" LOC = "R12";
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| 23 |
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NET "gpio0_out<25>" LOC = "T12";
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| 24 |
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NET "gpio0_out<26>" LOC = "R11";
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| 25 |
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NET "gpio0_out<27>" LOC = "R9";
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| 26 |
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NET "gpio0_out<28>" LOC = "T10";
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| 27 |
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NET "gpio0_out<2>" LOC = "L12";
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| 28 |
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NET "gpio0_out<3>" LOC = "N14";
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| 29 |
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NET "gpio0_out<4>" LOC = "P13";
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| 30 |
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NET "gpio0_out<5>" LOC = "N12";
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| 31 |
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NET "gpio0_out<6>" LOC = "P12";
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| 32 |
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NET "gpio0_out<7>" LOC = "P11";
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| 33 |
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NET "gpio0_out<8>" LOC = "E14";
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| 34 |
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NET "gpio0_out<9>" LOC = "G13";
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| 35 |
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NET "gpioA_in<0>" LOC = "F12";
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| 36 |
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NET "gpioA_in<10>" LOC = "L13";
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| 37 |
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NET "gpioA_in<1>" LOC = "G12";
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| 38 |
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NET "gpioA_in<2>" LOC = "H14";
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| 39 |
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NET "gpioA_in<30>" LOC = "M15";
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| 40 |
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NET "gpioA_in<31>" LOC = "M16";
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| 41 |
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NET "gpioA_in<3>" LOC = "H13";
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| 42 |
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NET "gpioA_in<4>" LOC = "J14";
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| 43 |
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NET "gpioA_in<5>" LOC = "J13";
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| 44 |
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NET "gpioA_in<6>" LOC = "K14";
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| 45 |
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NET "gpioA_in<7>" LOC = "K13";
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| 46 |
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NET "gpioA_in<8>" LOC = "M13";
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| 47 |
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NET "gpioA_in<9>" LOC = "M14";
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| 48 |
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NET "ram_address<10>" LOC = "E3";
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| 49 |
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NET "ram_address<11>" LOC = "E4";
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| 50 |
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NET "ram_address<12>" LOC = "G5";
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| 51 |
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NET "ram_address<13>" LOC = "H3";
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| 52 |
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NET "ram_address<14>" LOC = "H4";
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| 53 |
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NET "ram_address<15>" LOC = "J4";
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| 54 |
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NET "ram_address<16>" LOC = "J3";
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| 55 |
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NET "ram_address<17>" LOC = "K3";
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| 56 |
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NET "ram_address<18>" LOC = "K5";
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| 57 |
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NET "ram_address<19>" LOC = "L3";
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| 58 |
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NET "ram_address<2>" LOC = "L5";
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| 59 |
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NET "ram_address<3>" LOC = "N3";
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| 60 |
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NET "ram_address<4>" LOC = "M4";
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| 61 |
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NET "ram_address<5>" LOC = "M3";
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| 62 |
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NET "ram_address<6>" LOC = "L4";
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| 63 |
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NET "ram_address<7>" LOC = "G4";
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| 64 |
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NET "ram_address<8>" LOC = "F3";
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| 65 |
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NET "ram_address<9>" LOC = "F4";
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| 66 |
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NET "ram_ce1_n" LOC = "P7";
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| 67 |
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NET "ram_ce2_n" LOC = "N5";
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| 68 |
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NET "ram_data<0>" LOC = "P2";
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| 69 |
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NET "ram_data<10>" LOC = "G1";
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| 70 |
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NET "ram_data<11>" LOC = "F5";
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| 71 |
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NET "ram_data<12>" LOC = "C3";
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| 72 |
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NET "ram_data<13>" LOC = "K2";
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| 73 |
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NET "ram_data<14>" LOC = "M1";
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| 74 |
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NET "ram_data<15>" LOC = "N1";
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| 75 |
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NET "ram_data<16>" LOC = "N7";
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| 76 |
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NET "ram_data<17>" LOC = "T8";
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| 77 |
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NET "ram_data<18>" LOC = "R6";
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| 78 |
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NET "ram_data<19>" LOC = "T5";
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| 79 |
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NET "ram_data<1>" LOC = "N2";
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| 80 |
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NET "ram_data<20>" LOC = "R5";
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| 81 |
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NET "ram_data<21>" LOC = "C2";
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| 82 |
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NET "ram_data<22>" LOC = "C1";
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| 83 |
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NET "ram_data<23>" LOC = "B1";
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| 84 |
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NET "ram_data<24>" LOC = "D3";
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| 85 |
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NET "ram_data<25>" LOC = "P8";
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| 86 |
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NET "ram_data<26>" LOC = "F2";
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| 87 |
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NET "ram_data<27>" LOC = "H1";
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| 88 |
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NET "ram_data<28>" LOC = "J2";
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| 89 |
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NET "ram_data<29>" LOC = "L2";
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| 90 |
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NET "ram_data<2>" LOC = "M2";
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| 91 |
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NET "ram_data<30>" LOC = "P1";
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| 92 |
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NET "ram_data<31>" LOC = "R1";
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| 93 |
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NET "ram_data<3>" LOC = "K1";
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| 94 |
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NET "ram_data<4>" LOC = "J1";
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| 95 |
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NET "ram_data<5>" LOC = "G2";
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| 96 |
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NET "ram_data<6>" LOC = "E1";
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| 97 |
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NET "ram_data<7>" LOC = "D1";
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| 98 |
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NET "ram_data<8>" LOC = "D2";
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| 99 |
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NET "ram_data<9>" LOC = "E2";
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| 100 |
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NET "ram_lb1_n" LOC = "P6";
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| 101 |
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NET "ram_lb2_n" LOC = "P5";
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| 102 |
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NET "ram_oe_n" LOC = "K4";
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| 103 |
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NET "ram_ub1_n" LOC = "T4";
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| 104 |
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NET "ram_ub2_n" LOC = "R4";
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| 105 |
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NET "ram_we_n" LOC = "G3";
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| 106 |
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NET "reset" LOC = "L14";
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| 107 |
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NET "uart_read" LOC = "T13";
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| 108 |
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NET "uart_write" LOC = "R13";
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| 109 |
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#PACE: Start of PACE Area Constraints
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| 110 |
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#PACE: Start of PACE Prohibit Constraints
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| 111 |
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#PACE: End of Constraints generated by PACE
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