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---------------------------------------------------------------------
-- TITLE: Register Bank
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/2/01
-- FILENAME: reg_bank.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
--    Software 'as is' without warranty.  Author liable for nothing.
-- DESCRIPTION:
--    Implements a register bank with 32 registers that are 32-bits wide.
--    There are two read-ports and one write port.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.mlite_pack.all;
--library UNISIM;               --May need to uncomment for ModelSim
--use UNISIM.vcomponents.all;   --May need to uncomment for ModelSim
 
entity reg_bank is
   generic(memory_type : string := "XILINX_16X");
   port(clk            : in  std_logic;
        reset_in       : in  std_logic;
        pause          : in  std_logic;
        rs_index       : in  std_logic_vector(5 downto 0);
        rt_index       : in  std_logic_vector(5 downto 0);
        rd_index       : in  std_logic_vector(5 downto 0);
        reg_source_out : out std_logic_vector(31 downto 0);
        reg_target_out : out std_logic_vector(31 downto 0);
        reg_dest_new   : in  std_logic_vector(31 downto 0);
        intr_enable    : out std_logic);
end; --entity reg_bank
 
 
--------------------------------------------------------------------
-- The ram_block architecture attempts to use TWO dual-port memories.
-- Different FPGAs and ASICs need different implementations.
-- Choose one of the RAM implementations below.
-- I need feedback on this section!
--------------------------------------------------------------------
architecture ram_block of reg_bank is
   signal intr_enable_reg : std_logic;
   type ram_type is array(31 downto 0) of std_logic_vector(31 downto 0);
 
   --controls access to dual-port memories
   signal addr_read1, addr_read2 : std_logic_vector(4 downto 0);
   signal addr_write             : std_logic_vector(4 downto 0);
   signal data_out1, data_out2   : std_logic_vector(31 downto 0);
   signal write_enable           : std_logic;
 
begin
 
reg_proc: process(clk, rs_index, rt_index, rd_index, reg_dest_new,
      intr_enable_reg, data_out1, data_out2, reset_in, pause)
begin
   --setup for first dual-port memory
   if rs_index = "101110" then  --reg_epc CP0 14
      addr_read1 <= "00000";
   else
      addr_read1 <= rs_index(4 downto 0);
   end if;
   case rs_index is
   when "000000" => reg_source_out <= ZERO;
   when "101100" => reg_source_out <= ZERO(31 downto 1) & intr_enable_reg;
                    --interrupt vector address = 0x3c
   when "111111" => reg_source_out <= ZERO(31 downto 8) & "00111100";
   when others   => reg_source_out <= data_out1;
   end case;
 
   --setup for second dual-port memory
   addr_read2 <= rt_index(4 downto 0);
   case rt_index is
   when "000000" => reg_target_out <= ZERO;
   when others   => reg_target_out <= data_out2;
   end case;
 
   --setup write port for both dual-port memories
   if rd_index /= "000000" and rd_index /= "101100" and pause = '0' then
      write_enable <= '1';
   else
      write_enable <= '0';
   end if;
   if rd_index = "101110" then  --reg_epc CP0 14
      addr_write <= "00000";
   else
      addr_write <= rd_index(4 downto 0);
   end if;
 
   if reset_in = '1' then
      intr_enable_reg <= '0';
   elsif rising_edge(clk) then
      if rd_index = "101110" then     --reg_epc CP0 14
         intr_enable_reg <= '0';      --disable interrupts
      elsif rd_index = "101100" then
         intr_enable_reg <= reg_dest_new(0);
      end if;
   end if;
 
   intr_enable <= intr_enable_reg;
end process;
 
 
--------------------------------------------------------------
---- Pick only ONE of the dual-port RAM implementations below!
--------------------------------------------------------------
 
   -- Option #1
   -- One tri-port RAM, two read-ports, one write-port
   -- 32 registers 32-bits wide
   tri_port_mem:
   if memory_type = "TRI_PORT_X" generate
      ram_proc: process(clk, addr_read1, addr_read2,
            addr_write, reg_dest_new, write_enable)
      variable tri_port_ram : ram_type := (others => ZERO);
      begin
         data_out1 <= tri_port_ram(conv_integer(addr_read1));
         data_out2 <= tri_port_ram(conv_integer(addr_read2));
         if rising_edge(clk) then
            if write_enable = '1' then
               tri_port_ram(conv_integer(addr_write)) := reg_dest_new;
            end if;
         end if;
      end process;
   end generate; --tri_port_mem
 
 
   -- Option #2
   -- Two dual-port RAMs, each with one read-port and one write-port
   dual_port_mem:
   if memory_type = "DUAL_PORT_" generate
      ram_proc2: process(clk, addr_read1, addr_read2,
            addr_write, reg_dest_new, write_enable)
      variable dual_port_ram1 : ram_type := (others => ZERO);
      variable dual_port_ram2 : ram_type := (others => ZERO);
      begin
         data_out1 <= dual_port_ram1(conv_integer(addr_read1));
         data_out2 <= dual_port_ram2(conv_integer(addr_read2));
         if rising_edge(clk) then
            if write_enable = '1' then
               dual_port_ram1(conv_integer(addr_write)) := reg_dest_new;
               dual_port_ram2(conv_integer(addr_write)) := reg_dest_new;
            end if;
         end if;
      end process;
   end generate; --dual_port_mem
 
 
   -- Option #3
   -- RAM16X1D: 16 x 1 positive edge write, asynchronous read dual-port 
   -- distributed RAM for all Xilinx FPGAs
   -- From library UNISIM; use UNISIM.vcomponents.all;
   xilinx_16x1d:
   if memory_type = "XILINX_16X" generate
      signal data_out1A, data_out1B : std_logic_vector(31 downto 0);
      signal data_out2A, data_out2B : std_logic_vector(31 downto 0);
      signal weA, weB               : std_logic;
      signal no_connect             : std_logic_vector(127 downto 0);
   begin
      weA <= write_enable and not addr_write(4);  --lower 16 registers
      weB <= write_enable and addr_write(4);      --upper 16 registers
 
      reg_loop: for i in 0 to 31 generate
      begin
         --Read port 1 lower 16 registers
         reg_bit1a : RAM16X1D
         port map (
            WCLK  => clk,              -- Port A write clock input
            WE    => weA,              -- Port A write enable input
            A0    => addr_write(0),    -- Port A address[0] input bit
            A1    => addr_write(1),    -- Port A address[1] input bit
            A2    => addr_write(2),    -- Port A address[2] input bit
            A3    => addr_write(3),    -- Port A address[3] input bit
            D     => reg_dest_new(i),  -- Port A 1-bit data input
            DPRA0 => addr_read1(0),    -- Port B address[0] input bit
            DPRA1 => addr_read1(1),    -- Port B address[1] input bit
            DPRA2 => addr_read1(2),    -- Port B address[2] input bit
            DPRA3 => addr_read1(3),    -- Port B address[3] input bit
            DPO   => data_out1A(i),    -- Port B 1-bit data output
            SPO   => no_connect(i)     -- Port A 1-bit data output
         );
         --Read port 1 upper 16 registers
         reg_bit1b : RAM16X1D
         port map (
            WCLK  => clk,              -- Port A write clock input
            WE    => weB,              -- Port A write enable input
            A0    => addr_write(0),    -- Port A address[0] input bit
            A1    => addr_write(1),    -- Port A address[1] input bit
            A2    => addr_write(2),    -- Port A address[2] input bit
            A3    => addr_write(3),    -- Port A address[3] input bit
            D     => reg_dest_new(i),  -- Port A 1-bit data input
            DPRA0 => addr_read1(0),    -- Port B address[0] input bit
            DPRA1 => addr_read1(1),    -- Port B address[1] input bit
            DPRA2 => addr_read1(2),    -- Port B address[2] input bit
            DPRA3 => addr_read1(3),    -- Port B address[3] input bit
            DPO   => data_out1B(i),    -- Port B 1-bit data output
            SPO   => no_connect(32+i)  -- Port A 1-bit data output
         );
         --Read port 2 lower 16 registers
         reg_bit2a : RAM16X1D
         port map (
            WCLK  => clk,              -- Port A write clock input
            WE    => weA,              -- Port A write enable input
            A0    => addr_write(0),    -- Port A address[0] input bit
            A1    => addr_write(1),    -- Port A address[1] input bit
            A2    => addr_write(2),    -- Port A address[2] input bit
            A3    => addr_write(3),    -- Port A address[3] input bit
            D     => reg_dest_new(i),  -- Port A 1-bit data input
            DPRA0 => addr_read2(0),    -- Port B address[0] input bit
            DPRA1 => addr_read2(1),    -- Port B address[1] input bit
            DPRA2 => addr_read2(2),    -- Port B address[2] input bit
            DPRA3 => addr_read2(3),    -- Port B address[3] input bit
            DPO   => data_out2A(i),    -- Port B 1-bit data output
            SPO   => no_connect(64+i)  -- Port A 1-bit data output
         );
         --Read port 2 upper 16 registers
         reg_bit2b : RAM16X1D
         port map (
            WCLK  => clk,              -- Port A write clock input
            WE    => weB,              -- Port A write enable input
            A0    => addr_write(0),    -- Port A address[0] input bit
            A1    => addr_write(1),    -- Port A address[1] input bit
            A2    => addr_write(2),    -- Port A address[2] input bit
            A3    => addr_write(3),    -- Port A address[3] input bit
            D     => reg_dest_new(i),  -- Port A 1-bit data input
            DPRA0 => addr_read2(0),    -- Port B address[0] input bit
            DPRA1 => addr_read2(1),    -- Port B address[1] input bit
            DPRA2 => addr_read2(2),    -- Port B address[2] input bit
            DPRA3 => addr_read2(3),    -- Port B address[3] input bit
            DPO   => data_out2B(i),    -- Port B 1-bit data output
            SPO   => no_connect(96+i)  -- Port A 1-bit data output
         );
      end generate; --reg_loop
 
      data_out1 <= data_out1A when addr_read1(4)='0' else data_out1B;
      data_out2 <= data_out2A when addr_read2(4)='0' else data_out2B;
   end generate; --xilinx_16x1d
 
 
   -- Option #4
   -- RAM32X1D: 32 x 1 positive edge write, asynchronous read dual-port 
   -- distributed RAM for 5-LUT Xilinx FPGAs such as Virtex-5
   -- From library UNISIM; use UNISIM.vcomponents.all;
   xilinx_32x1d:
   if memory_type = "XILINX_32X" generate
      signal no_connect             : std_logic_vector(63 downto 0);
   begin
      reg_loop: for i in 0 to 31 generate
      begin
         --Read port 1
         reg_bit1 : RAM32X1D
         port map (
            WCLK  => clk,              -- Port A write clock input
            WE    => write_enable,     -- Port A write enable input
            A0    => addr_write(0),    -- Port A address[0] input bit
            A1    => addr_write(1),    -- Port A address[1] input bit
            A2    => addr_write(2),    -- Port A address[2] input bit
            A3    => addr_write(3),    -- Port A address[3] input bit
            A4    => addr_write(4),    -- Port A address[4] input bit
            D     => reg_dest_new(i),  -- Port A 1-bit data input
            DPRA0 => addr_read1(0),    -- Port B address[0] input bit
            DPRA1 => addr_read1(1),    -- Port B address[1] input bit
            DPRA2 => addr_read1(2),    -- Port B address[2] input bit
            DPRA3 => addr_read1(3),    -- Port B address[3] input bit
            DPRA4 => addr_read1(4),    -- Port B address[4] input bit
            DPO   => data_out1(i),     -- Port B 1-bit data output
            SPO   => no_connect(i)     -- Port A 1-bit data output
         );
         --Read port 2
         reg_bit2 : RAM32X1D
         port map (
            WCLK  => clk,              -- Port A write clock input
            WE    => write_enable,     -- Port A write enable input
            A0    => addr_write(0),    -- Port A address[0] input bit
            A1    => addr_write(1),    -- Port A address[1] input bit
            A2    => addr_write(2),    -- Port A address[2] input bit
            A3    => addr_write(3),    -- Port A address[3] input bit
            A4    => addr_write(4),    -- Port A address[4] input bit
            D     => reg_dest_new(i),  -- Port A 1-bit data input
            DPRA0 => addr_read2(0),    -- Port B address[0] input bit
            DPRA1 => addr_read2(1),    -- Port B address[1] input bit
            DPRA2 => addr_read2(2),    -- Port B address[2] input bit
            DPRA3 => addr_read2(3),    -- Port B address[3] input bit
            DPRA4 => addr_read2(4),    -- Port B address[4] input bit
            DPO   => data_out2(i),     -- Port B 1-bit data output
            SPO   => no_connect(32+i)  -- Port A 1-bit data output
         );
      end generate; --reg_loop
   end generate; --xilinx_32x1d
 
 
   -- Option #5
   -- Altera LPM_RAM_DP
   altera_mem:
   if memory_type = "ALTERA_LPM" generate
      signal clk_delayed : std_logic;
      signal addr_reg    : std_logic_vector(4 downto 0);
      signal data_reg    : std_logic_vector(31 downto 0);
      signal q1          : std_logic_vector(31 downto 0);
      signal q2          : std_logic_vector(31 downto 0);
   begin
      -- Altera dual port RAMs must have the addresses registered (sampled
      -- at the rising edge).  This is very unfortunate.
      -- Therefore, the dual port RAM read clock must delayed so that
      -- the read address signal can be sent from the mem_ctrl block.
      -- This solution also delays the how fast the registers are read so the 
      -- maximum clock speed is cut in half (12.5 MHz instead of 25 MHz).
 
      clk_delayed <= not clk;  --Could be delayed by 1/4 clock cycle instead
      dpram_bypass: process(clk, addr_write, reg_dest_new, write_enable)
      begin
         if rising_edge(clk) and write_enable = '1' then
            addr_reg <= addr_write;
            data_reg <= reg_dest_new;
         end if;
      end process; --dpram_bypass
 
      -- Bypass dpram if reading what was just written (Altera limitation)
      data_out1 <= q1 when addr_read1 /= addr_reg else data_reg;
      data_out2 <= q2 when addr_read2 /= addr_reg else data_reg;
 
      lpm_ram_dp_component1 : lpm_ram_dp
      generic map (
         LPM_WIDTH => 32,
         LPM_WIDTHAD => 5,
         --LPM_NUMWORDS => 0,
         LPM_INDATA => "REGISTERED",
         LPM_OUTDATA => "UNREGISTERED",
         LPM_RDADDRESS_CONTROL => "REGISTERED",
         LPM_WRADDRESS_CONTROL => "REGISTERED",
         LPM_FILE => "UNUSED",
         LPM_TYPE => "LPM_RAM_DP",
         USE_EAB  => "ON",
         INTENDED_DEVICE_FAMILY => "UNUSED",
         RDEN_USED => "FALSE",
         LPM_HINT => "UNUSED")
      port map (
         RDCLOCK   => clk_delayed,
         RDCLKEN   => '1',
         RDADDRESS => addr_read1,
         RDEN      => '1',
         DATA      => reg_dest_new,
         WRADDRESS => addr_write,
         WREN      => write_enable,
         WRCLOCK   => clk,
         WRCLKEN   => '1',
         Q         => q1);
      lpm_ram_dp_component2 : lpm_ram_dp
      generic map (
         LPM_WIDTH => 32,
         LPM_WIDTHAD => 5,
         --LPM_NUMWORDS => 0,
         LPM_INDATA => "REGISTERED",
         LPM_OUTDATA => "UNREGISTERED",
         LPM_RDADDRESS_CONTROL => "REGISTERED",
         LPM_WRADDRESS_CONTROL => "REGISTERED",
         LPM_FILE => "UNUSED",
         LPM_TYPE => "LPM_RAM_DP",
         USE_EAB  => "ON",
         INTENDED_DEVICE_FAMILY => "UNUSED",
         RDEN_USED => "FALSE",
         LPM_HINT => "UNUSED")
      port map (
         RDCLOCK   => clk_delayed,
         RDCLKEN   => '1',
         RDADDRESS => addr_read2,
         RDEN      => '1',
         DATA      => reg_dest_new,
         WRADDRESS => addr_write,
         WREN      => write_enable,
         WRCLOCK   => clk,
         WRCLKEN   => '1',
         Q         => q2);
   end generate; --altera_mem
 
end; --architecture ram_block

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[/] [plasma/] [trunk/] [vhdl/] [reg_bank.vhd] - Blame information for rev 406

Line No.	Rev	Author	Line
1	365	rhoads	`---------------------------------------------------------------------`
2			`-- TITLE: Register Bank`
3			`-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)`
4			`-- DATE CREATED: 2/2/01`
5			`-- FILENAME: reg_bank.vhd`
6			`-- PROJECT: Plasma CPU core`
7			`-- COPYRIGHT: Software placed into the public domain by the author.`
8			`-- Software 'as is' without warranty. Author liable for nothing.`
9			`-- DESCRIPTION:`
10			`-- Implements a register bank with 32 registers that are 32-bits wide.`
11			`-- There are two read-ports and one write port.`
12			`---------------------------------------------------------------------`
13			`library ieee;`
14			`use ieee.std_logic_1164.all;`
15			`use ieee.std_logic_unsigned.all;`
16			`use work.mlite_pack.all;`
17			`--library UNISIM; --May need to uncomment for ModelSim`
18			`--use UNISIM.vcomponents.all; --May need to uncomment for ModelSim`
19
20			`entity reg_bank is`
21			`generic(memory_type : string := "XILINX_16X");`
22			`port(clk : in std_logic;`
23			`reset_in : in std_logic;`
24			`pause : in std_logic;`
25			`rs_index : in std_logic_vector(5 downto 0);`
26			`rt_index : in std_logic_vector(5 downto 0);`
27			`rd_index : in std_logic_vector(5 downto 0);`
28			`reg_source_out : out std_logic_vector(31 downto 0);`
29			`reg_target_out : out std_logic_vector(31 downto 0);`
30			`reg_dest_new : in std_logic_vector(31 downto 0);`
31			`intr_enable : out std_logic);`
32			`end; --entity reg_bank`
33
34
35			`--------------------------------------------------------------------`
36			`-- The ram_block architecture attempts to use TWO dual-port memories.`
37			`-- Different FPGAs and ASICs need different implementations.`
38			`-- Choose one of the RAM implementations below.`
39			`-- I need feedback on this section!`
40			`--------------------------------------------------------------------`
41			`architecture ram_block of reg_bank is`
42			`signal intr_enable_reg : std_logic;`
43			`type ram_type is array(31 downto 0) of std_logic_vector(31 downto 0);`
44
45			`--controls access to dual-port memories`
46			`signal addr_read1, addr_read2 : std_logic_vector(4 downto 0);`
47			`signal addr_write : std_logic_vector(4 downto 0);`
48			`signal data_out1, data_out2 : std_logic_vector(31 downto 0);`
49			`signal write_enable : std_logic;`
50
51			`begin`
52
53			`reg_proc: process(clk, rs_index, rt_index, rd_index, reg_dest_new,`
54			`intr_enable_reg, data_out1, data_out2, reset_in, pause)`
55			`begin`
56			`--setup for first dual-port memory`
57			`if rs_index = "101110" then --reg_epc CP0 14`
58			`addr_read1 <= "00000";`
59			`else`
60			`addr_read1 <= rs_index(4 downto 0);`
61			`end if;`
62			`case rs_index is`
63			`when "000000" => reg_source_out <= ZERO;`
64			`when "101100" => reg_source_out <= ZERO(31 downto 1) & intr_enable_reg;`
65			`--interrupt vector address = 0x3c`
66			`when "111111" => reg_source_out <= ZERO(31 downto 8) & "00111100";`
67			`when others => reg_source_out <= data_out1;`
68			`end case;`
69
70			`--setup for second dual-port memory`
71			`addr_read2 <= rt_index(4 downto 0);`
72			`case rt_index is`
73			`when "000000" => reg_target_out <= ZERO;`
74			`when others => reg_target_out <= data_out2;`
75			`end case;`
76
77			`--setup write port for both dual-port memories`
78			`if rd_index /= "000000" and rd_index /= "101100" and pause = '0' then`
79			`write_enable <= '1';`
80			`else`
81			`write_enable <= '0';`
82			`end if;`
83			`if rd_index = "101110" then --reg_epc CP0 14`
84			`addr_write <= "00000";`
85			`else`
86			`addr_write <= rd_index(4 downto 0);`
87			`end if;`
88
89			`if reset_in = '1' then`
90			`intr_enable_reg <= '0';`
91			`elsif rising_edge(clk) then`
92			`if rd_index = "101110" then --reg_epc CP0 14`
93			`intr_enable_reg <= '0'; --disable interrupts`
94			`elsif rd_index = "101100" then`
95			`intr_enable_reg <= reg_dest_new(0);`
96			`end if;`
97			`end if;`
98
99			`intr_enable <= intr_enable_reg;`
100			`end process;`
101
102
103			`--------------------------------------------------------------`
104			`---- Pick only ONE of the dual-port RAM implementations below!`
105			`--------------------------------------------------------------`
106
107			`-- Option #1`
108			`-- One tri-port RAM, two read-ports, one write-port`
109			`-- 32 registers 32-bits wide`
110			`tri_port_mem:`
111			`if memory_type = "TRI_PORT_X" generate`
112			`ram_proc: process(clk, addr_read1, addr_read2,`
113			`addr_write, reg_dest_new, write_enable)`
114			`variable tri_port_ram : ram_type := (others => ZERO);`
115			`begin`
116			`data_out1 <= tri_port_ram(conv_integer(addr_read1));`
117			`data_out2 <= tri_port_ram(conv_integer(addr_read2));`
118			`if rising_edge(clk) then`
119			`if write_enable = '1' then`
120			`tri_port_ram(conv_integer(addr_write)) := reg_dest_new;`
121			`end if;`
122			`end if;`
123			`end process;`
124			`end generate; --tri_port_mem`
125
126
127			`-- Option #2`
128			`-- Two dual-port RAMs, each with one read-port and one write-port`
129			`dual_port_mem:`
130			`if memory_type = "DUAL_PORT_" generate`
131			`ram_proc2: process(clk, addr_read1, addr_read2,`
132			`addr_write, reg_dest_new, write_enable)`
133			`variable dual_port_ram1 : ram_type := (others => ZERO);`
134			`variable dual_port_ram2 : ram_type := (others => ZERO);`
135			`begin`
136			`data_out1 <= dual_port_ram1(conv_integer(addr_read1));`
137			`data_out2 <= dual_port_ram2(conv_integer(addr_read2));`
138			`if rising_edge(clk) then`
139			`if write_enable = '1' then`
140			`dual_port_ram1(conv_integer(addr_write)) := reg_dest_new;`
141			`dual_port_ram2(conv_integer(addr_write)) := reg_dest_new;`
142			`end if;`
143			`end if;`
144			`end process;`
145			`end generate; --dual_port_mem`
146
147
148			`-- Option #3`
149			`-- RAM16X1D: 16 x 1 positive edge write, asynchronous read dual-port`
150			`-- distributed RAM for all Xilinx FPGAs`
151			`-- From library UNISIM; use UNISIM.vcomponents.all;`
152			`xilinx_16x1d:`
153			`if memory_type = "XILINX_16X" generate`
154			`signal data_out1A, data_out1B : std_logic_vector(31 downto 0);`
155			`signal data_out2A, data_out2B : std_logic_vector(31 downto 0);`
156			`signal weA, weB : std_logic;`
157			`signal no_connect : std_logic_vector(127 downto 0);`
158			`begin`
159			`weA <= write_enable and not addr_write(4); --lower 16 registers`
160			`weB <= write_enable and addr_write(4); --upper 16 registers`
161
162			`reg_loop: for i in 0 to 31 generate`
163			`begin`
164			`--Read port 1 lower 16 registers`
165			`reg_bit1a : RAM16X1D`
166			`port map (`
167			`WCLK => clk, -- Port A write clock input`
168			`WE => weA, -- Port A write enable input`
169			`A0 => addr_write(0), -- Port A address[0] input bit`
170			`A1 => addr_write(1), -- Port A address[1] input bit`
171			`A2 => addr_write(2), -- Port A address[2] input bit`
172			`A3 => addr_write(3), -- Port A address[3] input bit`
173			`D => reg_dest_new(i), -- Port A 1-bit data input`
174			`DPRA0 => addr_read1(0), -- Port B address[0] input bit`
175			`DPRA1 => addr_read1(1), -- Port B address[1] input bit`
176			`DPRA2 => addr_read1(2), -- Port B address[2] input bit`
177			`DPRA3 => addr_read1(3), -- Port B address[3] input bit`
178			`DPO => data_out1A(i), -- Port B 1-bit data output`
179			`SPO => no_connect(i) -- Port A 1-bit data output`
180			`);`
181			`--Read port 1 upper 16 registers`
182			`reg_bit1b : RAM16X1D`
183			`port map (`
184			`WCLK => clk, -- Port A write clock input`
185			`WE => weB, -- Port A write enable input`
186			`A0 => addr_write(0), -- Port A address[0] input bit`
187			`A1 => addr_write(1), -- Port A address[1] input bit`
188			`A2 => addr_write(2), -- Port A address[2] input bit`
189			`A3 => addr_write(3), -- Port A address[3] input bit`
190			`D => reg_dest_new(i), -- Port A 1-bit data input`
191			`DPRA0 => addr_read1(0), -- Port B address[0] input bit`
192			`DPRA1 => addr_read1(1), -- Port B address[1] input bit`
193			`DPRA2 => addr_read1(2), -- Port B address[2] input bit`
194			`DPRA3 => addr_read1(3), -- Port B address[3] input bit`
195			`DPO => data_out1B(i), -- Port B 1-bit data output`
196			`SPO => no_connect(32+i) -- Port A 1-bit data output`
197			`);`
198			`--Read port 2 lower 16 registers`
199			`reg_bit2a : RAM16X1D`
200			`port map (`
201			`WCLK => clk, -- Port A write clock input`
202			`WE => weA, -- Port A write enable input`
203			`A0 => addr_write(0), -- Port A address[0] input bit`
204			`A1 => addr_write(1), -- Port A address[1] input bit`
205			`A2 => addr_write(2), -- Port A address[2] input bit`
206			`A3 => addr_write(3), -- Port A address[3] input bit`
207			`D => reg_dest_new(i), -- Port A 1-bit data input`
208			`DPRA0 => addr_read2(0), -- Port B address[0] input bit`
209			`DPRA1 => addr_read2(1), -- Port B address[1] input bit`
210			`DPRA2 => addr_read2(2), -- Port B address[2] input bit`
211			`DPRA3 => addr_read2(3), -- Port B address[3] input bit`
212			`DPO => data_out2A(i), -- Port B 1-bit data output`
213			`SPO => no_connect(64+i) -- Port A 1-bit data output`
214			`);`
215			`--Read port 2 upper 16 registers`
216			`reg_bit2b : RAM16X1D`
217			`port map (`
218			`WCLK => clk, -- Port A write clock input`
219			`WE => weB, -- Port A write enable input`
220			`A0 => addr_write(0), -- Port A address[0] input bit`
221			`A1 => addr_write(1), -- Port A address[1] input bit`
222			`A2 => addr_write(2), -- Port A address[2] input bit`
223			`A3 => addr_write(3), -- Port A address[3] input bit`
224			`D => reg_dest_new(i), -- Port A 1-bit data input`
225			`DPRA0 => addr_read2(0), -- Port B address[0] input bit`
226			`DPRA1 => addr_read2(1), -- Port B address[1] input bit`
227			`DPRA2 => addr_read2(2), -- Port B address[2] input bit`
228			`DPRA3 => addr_read2(3), -- Port B address[3] input bit`
229			`DPO => data_out2B(i), -- Port B 1-bit data output`
230			`SPO => no_connect(96+i) -- Port A 1-bit data output`
231			`);`
232			`end generate; --reg_loop`
233
234			`data_out1 <= data_out1A when addr_read1(4)='0' else data_out1B;`
235			`data_out2 <= data_out2A when addr_read2(4)='0' else data_out2B;`
236			`end generate; --xilinx_16x1d`
237
238
239			`-- Option #4`
240	397	rhoads	`-- RAM32X1D: 32 x 1 positive edge write, asynchronous read dual-port`
241			`-- distributed RAM for 5-LUT Xilinx FPGAs such as Virtex-5`
242			`-- From library UNISIM; use UNISIM.vcomponents.all;`
243			`xilinx_32x1d:`
244			`if memory_type = "XILINX_32X" generate`
245			`signal no_connect : std_logic_vector(63 downto 0);`
246			`begin`
247			`reg_loop: for i in 0 to 31 generate`
248			`begin`
249			`--Read port 1`
250			`reg_bit1 : RAM32X1D`
251			`port map (`
252			`WCLK => clk, -- Port A write clock input`
253			`WE => write_enable, -- Port A write enable input`
254			`A0 => addr_write(0), -- Port A address[0] input bit`
255			`A1 => addr_write(1), -- Port A address[1] input bit`
256			`A2 => addr_write(2), -- Port A address[2] input bit`
257			`A3 => addr_write(3), -- Port A address[3] input bit`
258			`A4 => addr_write(4), -- Port A address[4] input bit`
259			`D => reg_dest_new(i), -- Port A 1-bit data input`
260			`DPRA0 => addr_read1(0), -- Port B address[0] input bit`
261			`DPRA1 => addr_read1(1), -- Port B address[1] input bit`
262			`DPRA2 => addr_read1(2), -- Port B address[2] input bit`
263			`DPRA3 => addr_read1(3), -- Port B address[3] input bit`
264			`DPRA4 => addr_read1(4), -- Port B address[4] input bit`
265			`DPO => data_out1(i), -- Port B 1-bit data output`
266			`SPO => no_connect(i) -- Port A 1-bit data output`
267			`);`
268			`--Read port 2`
269			`reg_bit2 : RAM32X1D`
270			`port map (`
271			`WCLK => clk, -- Port A write clock input`
272			`WE => write_enable, -- Port A write enable input`
273			`A0 => addr_write(0), -- Port A address[0] input bit`
274			`A1 => addr_write(1), -- Port A address[1] input bit`
275			`A2 => addr_write(2), -- Port A address[2] input bit`
276			`A3 => addr_write(3), -- Port A address[3] input bit`
277			`A4 => addr_write(4), -- Port A address[4] input bit`
278			`D => reg_dest_new(i), -- Port A 1-bit data input`
279			`DPRA0 => addr_read2(0), -- Port B address[0] input bit`
280			`DPRA1 => addr_read2(1), -- Port B address[1] input bit`
281			`DPRA2 => addr_read2(2), -- Port B address[2] input bit`
282			`DPRA3 => addr_read2(3), -- Port B address[3] input bit`
283			`DPRA4 => addr_read2(4), -- Port B address[4] input bit`
284			`DPO => data_out2(i), -- Port B 1-bit data output`
285			`SPO => no_connect(32+i) -- Port A 1-bit data output`
286			`);`
287			`end generate; --reg_loop`
288			`end generate; --xilinx_32x1d`
289
290
291			`-- Option #5`
292	365	rhoads	`-- Altera LPM_RAM_DP`
293			`altera_mem:`
294			`if memory_type = "ALTERA_LPM" generate`
295			`signal clk_delayed : std_logic;`
296			`signal addr_reg : std_logic_vector(4 downto 0);`
297			`signal data_reg : std_logic_vector(31 downto 0);`
298			`signal q1 : std_logic_vector(31 downto 0);`
299			`signal q2 : std_logic_vector(31 downto 0);`
300			`begin`
301			`-- Altera dual port RAMs must have the addresses registered (sampled`
302			`-- at the rising edge). This is very unfortunate.`
303			`-- Therefore, the dual port RAM read clock must delayed so that`
304			`-- the read address signal can be sent from the mem_ctrl block.`
305			`-- This solution also delays the how fast the registers are read so the`
306			`-- maximum clock speed is cut in half (12.5 MHz instead of 25 MHz).`
307
308			`clk_delayed <= not clk; --Could be delayed by 1/4 clock cycle instead`
309	376	rhoads	`dpram_bypass: process(clk, addr_write, reg_dest_new, write_enable)`
310	365	rhoads	`begin`
311			`if rising_edge(clk) and write_enable = '1' then`
312			`addr_reg <= addr_write;`
313			`data_reg <= reg_dest_new;`
314			`end if;`
315			`end process; --dpram_bypass`
316
317			`-- Bypass dpram if reading what was just written (Altera limitation)`
318			`data_out1 <= q1 when addr_read1 /= addr_reg else data_reg;`
319			`data_out2 <= q2 when addr_read2 /= addr_reg else data_reg;`
320
321			`lpm_ram_dp_component1 : lpm_ram_dp`
322			`generic map (`
323			`LPM_WIDTH => 32,`
324			`LPM_WIDTHAD => 5,`
325			`--LPM_NUMWORDS => 0,`
326			`LPM_INDATA => "REGISTERED",`
327			`LPM_OUTDATA => "UNREGISTERED",`
328			`LPM_RDADDRESS_CONTROL => "REGISTERED",`
329			`LPM_WRADDRESS_CONTROL => "REGISTERED",`
330			`LPM_FILE => "UNUSED",`
331			`LPM_TYPE => "LPM_RAM_DP",`
332			`USE_EAB => "ON",`
333			`INTENDED_DEVICE_FAMILY => "UNUSED",`
334			`RDEN_USED => "FALSE",`
335			`LPM_HINT => "UNUSED")`
336			`port map (`
337			`RDCLOCK => clk_delayed,`
338			`RDCLKEN => '1',`
339			`RDADDRESS => addr_read1,`
340			`RDEN => '1',`
341			`DATA => reg_dest_new,`
342			`WRADDRESS => addr_write,`
343			`WREN => write_enable,`
344			`WRCLOCK => clk,`
345			`WRCLKEN => '1',`
346			`Q => q1);`
347			`lpm_ram_dp_component2 : lpm_ram_dp`
348			`generic map (`
349			`LPM_WIDTH => 32,`
350			`LPM_WIDTHAD => 5,`
351			`--LPM_NUMWORDS => 0,`
352			`LPM_INDATA => "REGISTERED",`
353			`LPM_OUTDATA => "UNREGISTERED",`
354			`LPM_RDADDRESS_CONTROL => "REGISTERED",`
355			`LPM_WRADDRESS_CONTROL => "REGISTERED",`
356			`LPM_FILE => "UNUSED",`
357			`LPM_TYPE => "LPM_RAM_DP",`
358			`USE_EAB => "ON",`
359			`INTENDED_DEVICE_FAMILY => "UNUSED",`
360			`RDEN_USED => "FALSE",`
361			`LPM_HINT => "UNUSED")`
362			`port map (`
363			`RDCLOCK => clk_delayed,`
364			`RDCLKEN => '1',`
365			`RDADDRESS => addr_read2,`
366			`RDEN => '1',`
367			`DATA => reg_dest_new,`
368			`WRADDRESS => addr_write,`
369			`WREN => write_enable,`
370			`WRCLOCK => clk,`
371			`WRCLKEN => '1',`
372			`Q => q2);`
373			`end generate; --altera_mem`
374
375			`end; --architecture ram_block`