OpenCores
URL https://opencores.org/ocsvn/plasma/plasma/trunk

Subversion Repositories plasma

[/] [plasma/] [trunk/] [vhdl/] [uart.vhd] - Blame information for rev 417

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 47 rhoads
---------------------------------------------------------------------
2
-- TITLE: UART
3
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
4
-- DATE CREATED: 5/29/02
5
-- FILENAME: uart.vhd
6
-- PROJECT: Plasma CPU core
7
-- COPYRIGHT: Software placed into the public domain by the author.
8
--    Software 'as is' without warranty.  Author liable for nothing.
9
-- DESCRIPTION:
10
--    Implements the UART.
11
---------------------------------------------------------------------
12
library ieee;
13
use ieee.std_logic_1164.all;
14
use ieee.std_logic_misc.all;
15
use ieee.std_logic_arith.all;
16
use ieee.std_logic_textio.all;
17 75 rhoads
use ieee.std_logic_unsigned.all;
18 47 rhoads
use std.textio.all;
19
use work.mlite_pack.all;
20
 
21
entity uart is
22 48 rhoads
   generic(log_file : string := "UNUSED");
23 139 rhoads
   port(clk          : in std_logic;
24
        reset        : in std_logic;
25
        enable_read  : in std_logic;
26
        enable_write : in std_logic;
27
        data_in      : in std_logic_vector(7 downto 0);
28
        data_out     : out std_logic_vector(7 downto 0);
29
        uart_read    : in std_logic;
30
        uart_write   : out std_logic;
31
        busy_write   : out std_logic;
32
        data_avail   : out std_logic);
33
end; --entity uart
34 47 rhoads
 
35
architecture logic of uart is
36 139 rhoads
   signal delay_write_reg : std_logic_vector(9 downto 0);
37
   signal bits_write_reg  : std_logic_vector(3 downto 0);
38
   signal data_write_reg  : std_logic_vector(8 downto 0);
39
   signal delay_read_reg  : std_logic_vector(9 downto 0);
40
   signal bits_read_reg   : std_logic_vector(3 downto 0);
41
   signal data_read_reg   : std_logic_vector(7 downto 0);
42 279 rhoads
   signal data_save_reg   : std_logic_vector(17 downto 0);
43 139 rhoads
   signal busy_write_sig  : std_logic;
44 334 rhoads
   signal read_value_reg  : std_logic_vector(6 downto 0);
45 139 rhoads
   signal uart_read2      : std_logic;
46
 
47 48 rhoads
begin
48 47 rhoads
 
49 139 rhoads
uart_proc: process(clk, reset, enable_read, enable_write, data_in,
50
                   data_write_reg, bits_write_reg, delay_write_reg,
51
                   data_read_reg, bits_read_reg, delay_read_reg,
52 180 rhoads
                   data_save_reg, read_value_reg, uart_read2,
53
                   busy_write_sig, uart_read)
54 139 rhoads
   constant COUNT_VALUE : std_logic_vector(9 downto 0) :=
55
--      "0100011110";  --33MHz/2/57600Hz = 0x11e
56
--      "1101100100";  --50MHz/57600Hz = 0x364
57 180 rhoads
      "0110110010";  --25MHz/57600Hz = 0x1b2 -- Plasma IF uses div2
58 334 rhoads
--      "0011011001";  --12.5MHz/57600Hz = 0xd9
59 139 rhoads
--      "0000000100";  --for debug (shorten read_value_reg)
60 47 rhoads
begin
61 139 rhoads
   uart_read2 <= read_value_reg(read_value_reg'length - 1);
62 47 rhoads
 
63
   if reset = '1' then
64 139 rhoads
      data_write_reg  <= ZERO(8 downto 1) & '1';
65
      bits_write_reg  <= "0000";
66
      delay_write_reg <= ZERO(9 downto 0);
67 334 rhoads
      read_value_reg  <= ONES(read_value_reg'length-1 downto 0);
68 139 rhoads
      data_read_reg   <= ZERO(7 downto 0);
69
      bits_read_reg   <= "0000";
70
      delay_read_reg  <= ZERO(9 downto 0);
71 279 rhoads
      data_save_reg   <= ZERO(17 downto 0);
72 55 rhoads
   elsif rising_edge(clk) then
73 47 rhoads
 
74 139 rhoads
      --Write UART
75
      if bits_write_reg = "0000" then               --nothing left to write?
76
         if enable_write = '1' then
77
            delay_write_reg <= ZERO(9 downto 0);    --delay before next bit
78
            bits_write_reg <= "1010";               --number of bits to write
79
            data_write_reg <= data_in & '0';        --remember data & start bit
80
         end if;
81
      else
82
         if delay_write_reg /= COUNT_VALUE then
83
            delay_write_reg <= delay_write_reg + 1; --delay before next bit
84
         else
85
            delay_write_reg <= ZERO(9 downto 0);    --reset delay
86
            bits_write_reg <= bits_write_reg - 1;   --bits left to write
87
            data_write_reg <= '1' & data_write_reg(8 downto 1);
88
         end if;
89
      end if;
90
 
91
      --Average uart_read signal
92
      if uart_read = '1' then
93
         if read_value_reg /= ONES(read_value_reg'length - 1 downto 0) then
94
            read_value_reg <= read_value_reg + 1;
95
         end if;
96
      else
97
         if read_value_reg /= ZERO(read_value_reg'length - 1 downto 0) then
98
            read_value_reg <= read_value_reg - 1;
99
         end if;
100
      end if;
101
 
102
      --Read UART
103
      if delay_read_reg = ZERO(9 downto 0) then     --done delay for read?
104
         if bits_read_reg = "0000" then             --nothing left to read?
105
            if uart_read2 = '0' then                --wait for start bit
106
               delay_read_reg <= '0' & COUNT_VALUE(9 downto 1);  --half period
107
               bits_read_reg <= "1001";             --bits left to read
108
            end if;
109
         else
110
            delay_read_reg <= COUNT_VALUE;          --initialize delay
111
            bits_read_reg <= bits_read_reg - 1;     --bits left to read
112
            data_read_reg <= uart_read2 & data_read_reg(7 downto 1);
113
         end if;
114
      else
115
         delay_read_reg <= delay_read_reg - 1;      --delay
116
      end if;
117
 
118 279 rhoads
      --Control character buffer
119 139 rhoads
      if bits_read_reg = "0000" and delay_read_reg = COUNT_VALUE then
120 279 rhoads
         if data_save_reg(8) = '0' or
121
               (enable_read = '1' and data_save_reg(17) = '0') then
122
            --Empty buffer
123
            data_save_reg(8 downto 0) <= '1' & data_read_reg;
124
         else
125
            --Second character in buffer
126
            data_save_reg(17 downto 9) <= '1' & data_read_reg;
127
            if enable_read = '1' then
128
               data_save_reg(8 downto 0) <= data_save_reg(17 downto 9);
129
            end if;
130
         end if;
131 139 rhoads
      elsif enable_read = '1' then
132 279 rhoads
         data_save_reg(17) <= '0';                  --data_available
133
         data_save_reg(8 downto 0) <= data_save_reg(17 downto 9);
134 139 rhoads
      end if;
135
   end if;  --rising_edge(clk)
136
 
137
   uart_write <= data_write_reg(0);
138 180 rhoads
   if bits_write_reg /= "0000"
139
-- Comment out the following line for full UART simulation (much slower)
140
   and log_file = "UNUSED"
141
   then
142 139 rhoads
      busy_write_sig <= '1';
143 47 rhoads
   else
144 139 rhoads
      busy_write_sig <= '0';
145 47 rhoads
   end if;
146 139 rhoads
   busy_write <= busy_write_sig;
147
   data_avail <= data_save_reg(8);
148
   data_out <= data_save_reg(7 downto 0);
149
 
150
end process; --uart_proc
151 47 rhoads
 
152 180 rhoads
-- synthesis_off
153 48 rhoads
   uart_logger:
154
   if log_file /= "UNUSED" generate
155 139 rhoads
      uart_proc: process(clk, enable_write, data_in)
156
         file store_file : text open write_mode is log_file;
157 48 rhoads
         variable hex_file_line : line;
158
         variable c : character;
159
         variable index : natural;
160
         variable line_length : natural := 0;
161
      begin
162 139 rhoads
         if rising_edge(clk) and busy_write_sig = '0' then
163
            if enable_write = '1' then
164
               index := conv_integer(data_in(6 downto 0));
165 48 rhoads
               if index /= 10 then
166
                  c := character'val(index);
167
                  write(hex_file_line, c);
168
                  line_length := line_length + 1;
169
               end if;
170
               if index = 10 or line_length >= 72 then
171 180 rhoads
--The following line may have to be commented out for synthesis
172 48 rhoads
                  writeline(store_file, hex_file_line);
173
                  line_length := 0;
174
               end if;
175
            end if; --uart_sel
176
         end if; --rising_edge(clk)
177
      end process; --uart_proc
178
   end generate; --uart_logger
179 180 rhoads
-- synthesis_on
180 48 rhoads
 
181 47 rhoads
end; --architecture logic

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.