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__alexs__ |
-- --------------------------------------------------------------------------
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-- >>>>>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<<
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-- --------------------------------------------------------------------------
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-- TITLE: Multiplier core
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-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
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-- Alex Schoenberger (Alex.Schoenberger@ies.tu-darmstadt.de)
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-- COMMENT: bit-pair algorithm for multiplication
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--
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-- www.ies.tu-darmstadt.de
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-- TU Darmstadt
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-- Institute for Integrated Systems
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-- Merckstr. 25
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--
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-- 64283 Darmstadt - GERMANY
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-- --------------------------------------------------------------------------
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-- PROJECT: Plasma CPU core with FPU
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-- FILENAME: mul_core.vhd
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-- --------------------------------------------------------------------------
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-- COPYRIGHT:
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-- This project is distributed by GPLv2.0
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-- Software placed into the public domain by the author.
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-- Software 'as is' without warranty. Author liable for nothing.
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-- --------------------------------------------------------------------------
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-- DESCRIPTION:
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-- long64 answer = 0;
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-- for(i = 0; i < 32; ++i)
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-- {
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-- answer = (answer >> 1) + (((b&1)?a:0) << 31);
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-- b = b >> 1;
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-- }
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--
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-- SYNTHESIZABLE
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--
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----------------------------------------------------------------------------
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-- Revision History
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-- --------------------------------------------------------------------------
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-- Revision Date Author CHANGES
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-- 1.0 7/2014 AS initial
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-- --------------------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.ALL;
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use IEEE.numeric_std.ALL;
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entity mul_core is
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port(
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clk : in std_logic;
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rst : in std_logic;
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start : in std_logic;
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busy : out std_logic;
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rdy : out std_logic;
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sign_flag : in std_logic;
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a : in std_logic_vector(31 downto 0);
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b : in std_logic_vector(31 downto 0);
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c : out std_logic_vector(63 downto 0)
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);
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end entity mul_core;
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-- _____ _____ _ _ _____ _______ ______ _____ _______ _ _ _____ ______
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-- /\ | __ \ / ____| | | |_ _|__ __| ____/ ____|__ __| | | | __ \| ____|
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-- / \ | |__) | | | |__| | | | | | | |__ | | | | | | | | |__) | |__
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-- / /\ \ | _ /| | | __ | | | | | | __|| | | | | | | | _ /| __|
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-- / ____ \| | \ \| |____| | | |_| |_ | | | |___| |____ | | | |__| | | \ \| |____
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-- /_/ \_\_| \_\\_____|_| |_|_____| |_| |______\_____| |_| \____/|_| \_\______|
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architecture mul_core_structure of mul_core is
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-- _ _ _ ___ _ _ ___
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-- | |\ | |__] | | |
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-- | | \| | |__| |
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alias flag_b_neg : std_logic is b(31); -- operand B is negative
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signal a_convert : std_logic_vector(31 downto 0); -- twoscomplement of operand A
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signal b_convert : std_logic_vector(31 downto 0); -- twoscomplement of operand B
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signal a_input : std_logic_vector(31 downto 0); -- final input of operand A
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signal b_input : std_logic_vector(31 downto 0); -- final input of operand B
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signal i_input : std_logic_vector(31 downto 0); -- first intermediate result
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-- ____ ____ ____ _ ____ ___ ____ ____ ____
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-- |__/ |___ | __ | [__ | |___ |__/ [__
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-- | \ |___ |__] | ___] | |___ | \ ___]
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signal i_lower, reg_lower : std_logic_vector(31 downto 0);
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signal i_upper, reg_upper : std_logic_vector(31 downto 0);
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signal reg_adder : std_logic_vector(31 downto 0);
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signal reg_sign : std_logic;
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-- ___ ____ ___ ____ ___ ____ ___ _ _
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-- | \ |__| | |__| |__] |__| | |__|
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-- |__/ | | | | | | | | | | |
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signal i_sum_in : std_logic_vector(31 downto 0); -- input of summary
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signal i_sum : std_logic_vector(32 downto 0); -- intermediate sum, extended with carry
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alias sum_en : std_logic is reg_lower(0); -- enable summary if current LSB is '1'
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alias a_msb : std_logic is reg_upper(31); -- for signed multiplication detect leading ones
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alias b_msb : std_logic is i_sum_in(31); -- for signed multiplication
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-- ____ ____ _ _ ___ ____ ____ _ ___ ____ ___ _ _
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-- | | | |\ | | |__/ | | | |__] |__| | |__|
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-- |___ |__| | \| | | \ |__| |___ | | | | | |
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type t_mul_state is ( s_IDLE, s_WORK );
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signal i_state, state : t_mul_state; -- state variable
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type t_mul_flags is
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record
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input_en : std_logic;
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work_en : std_logic;
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cnt_en : std_logic;
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cnt_done : std_logic;
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end record;
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signal flags : t_mul_flags; -- internal flags
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-- ____ ____ _ _ _ _ ___ ____ ____
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-- | | | | | |\ | | |___ |__/
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-- |___ |__| |__| | \| | |___ | \
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signal mul_counter : std_logic_vector(4 downto 0); -- 2**5 = 32 clock cycles for multiplication
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begin
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-- synthesis translate_off
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-- ____ ____ _ _ _ ___ _ _ ____ _ _ ____ ____ _ _
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-- [__ |__| |\ | | | \_/ | |__| |___ | |_/
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-- ___] | | | \| | | | |___ | | |___ |___ | \_
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sanity_process:process( a, b )
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begin
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assert (not((a = x"8000_0000") and (sign_flag = '1'))) report "WARNING: operand A of MUL-CORE is 0x8000_0000, result will be erroneous!" severity warning;
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assert (not((b = x"8000_0000") and (sign_flag = '1'))) report "WARNING: operand B of MUL-CORE is 0x8000_0000, result will be erroneous!" severity warning;
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end process;
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-- synthesis translate_on
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-- _ _ _ ___ _ _ ___
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-- | |\ | |__] | | |
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-- | | \| | |__| |
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--
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-- calculate twoscomplement
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--
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a_convert <= std_logic_vector( unsigned(not a) + to_unsigned(1, 32) );
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b_convert <= std_logic_vector( unsigned(not b) + to_unsigned(1, 32) );
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--
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-- for signed multiplication and negative operand B take twoscomplements
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--
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a_input <= a_convert when (flag_b_neg and sign_flag) = '1' else a;
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b_input <= b_convert when (flag_b_neg and sign_flag) = '1' else b;
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--
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-- if LSB of operand B is '1' the first intermediate result is operand A
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--
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i_input <= a_input when b_input(0) = '1' else (others => '0');
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-- ____ ____ ____ _ ____ ___ ____ ____ ____
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-- |__/ |___ | __ | [__ | |___ |__/ [__
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-- | \ |___ |__] | ___] | |___ | \ ___]
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--
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-- reg_upper & reg_lower compose result
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-- reg_adder contain (to shift) adder constant
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-- reg_sign indicates signed multiplication
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--
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-- counter value and state variable
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--
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mul_registers:
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process( clk )
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begin
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if rising_edge( clk ) then
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if rst = '1' then -- << RESET ACTIVE
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reg_lower <= (others => '0');
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reg_upper <= (others => '0');
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reg_adder <= (others => '0');
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reg_sign <= '0';
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mul_counter <= (others => '0');
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state <= s_IDLE;
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else -- << RISING EDGE OF CLK
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-- ############ FIRST INPUT ################
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if flags.input_en = '1' then
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reg_sign <= sign_flag;
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reg_adder <= a_input;
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reg_lower <= i_input(0) & b_input(31 downto 1); -- shift first intermediate result
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reg_upper <= (sign_flag and i_input(31)) & i_input(31 downto 1);
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else
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-- ########## CALCULATION ################
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if flags.work_en = '1' then
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reg_lower <= i_lower;
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reg_upper <= i_upper;
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end if;
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end if;
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if flags.cnt_en = '1' then
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mul_counter <= std_logic_vector(unsigned(mul_counter) + to_unsigned(1, 5));
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else
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mul_counter <= (others => '0');
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end if;
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state <= i_state; -- always active
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end if;
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end if;
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end process;
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-- ___ ____ ___ ____ ___ ____ ___ _ _
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-- | \ |__| | |__| |__] |__| | |__|
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-- |__/ | | | | | | | | | | |
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--
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-- get intermediate summand
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--
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i_sum_in <= reg_adder when sum_en = '1' else (others => '0');
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--
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-- calculate intermediate sum
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--
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i_sum <= std_logic_vector( unsigned((reg_sign and a_msb) & reg_upper) -- for signed multiplication extend with MSB of reg upper
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+
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unsigned((reg_sign and b_msb) & i_sum_in) ); -- for signed multiplication extend with MSB of i_sum_in
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--
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-- shift intermediate result
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--
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i_upper <= i_sum(32 downto 1); -- get upper bits
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i_lower <= i_sum(0) & reg_lower(31 downto 1); -- get LSB and shift lower bits
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-- ____ ____ _ _ ___ ____ ____ _ ___ ____ ___ _ _
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-- | | | |\ | | |__/ | | | |__] |__| | |__|
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-- |___ |__| | \| | | \ |__| |___ | | | | | |
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mul_control:
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process( start, state, flags.cnt_done )
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begin
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-- ######## DEFAULT VALUES
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--
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-- intern flags
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--
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flags.input_en <= '0'; -- no input
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flags.work_en <= '0'; -- no calculation
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flags.cnt_en <= '0'; -- no counting
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--
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-- state variable
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--
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i_state <= s_IDLE; -- waiting for commands
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--
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-- outputs
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--
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busy <= '0'; -- no calculation indication
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rdy <= '0'; -- no result indication
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-- ######### CONTROL LOGIC
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case state is
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when s_IDLE =>
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if start = '1' then
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busy <= '1';
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flags.input_en <= '1';
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flags.cnt_en <= '1';
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i_state <= s_WORK;
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end if;
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when s_WORK =>
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busy <= '1';
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if flags.cnt_done = '1' then -- finish calculation
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rdy <= '1';
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else
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flags.work_en <= '1';
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flags.cnt_en <= '1';
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i_state <= s_WORK;
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end if;
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when others =>
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end case;
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end process;
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-- ____ ____ _ _ _ _ ___ ____ ____
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-- | | | | | |\ | | |___ |__/
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-- |___ |__| |__| | \| | |___ | \
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--
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-- get counter flag
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--
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flags.cnt_done <= '1' when mul_counter = "00000" else '0';
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-- ____ _ _ ___ ___ _ _ ___
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-- | | | | | |__] | | |
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-- |__| |__| | | |__| |
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c <= reg_upper & reg_lower;
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end architecture mul_core_structure;
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