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__alexs__ |
-- --------------------------------------------------------------------------
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-- >>>>>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<<
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-- --------------------------------------------------------------------------
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-- TITLE: Plasma DATAPATH
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-- AUTHOR: Alex Schoenberger (Alex.Schoenberger@ies.tu-darmstadt.de)
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-- COMMENT: This project is based on Plasma CPU core by Steve Rhoads
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--
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-- www.ies.tu-darmstadt.de
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-- TU Darmstadt
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-- Institute for Integrated Systems
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-- Merckstr. 25
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--
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-- 64283 Darmstadt - GERMANY
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-- --------------------------------------------------------------------------
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-- PROJECT: Plasma CPU core with FPU
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-- FILENAME: plasma_datapath.vhd
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-- --------------------------------------------------------------------------
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-- COPYRIGHT:
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-- This project is distributed by GPLv2.0
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-- Software placed into the public domain by the author.
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-- Software 'as is' without warranty. Author liable for nothing.
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-- --------------------------------------------------------------------------
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-- DESCRIPTION:
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-- datapath of plasma core
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--
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-- SYNTHESIZABLE
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--
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----------------------------------------------------------------------------
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-- Revision History
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-- --------------------------------------------------------------------------
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-- Revision Date Author CHANGES
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-- 1.0 4/2014 AS initial
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-- 2.0 12/2014 AS separated into MIPS1 simple architecture
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-- and with FPU included
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-- 3.0 05/2015 AS made generic port, included immediate mux
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-- --------------------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.ALL;
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library PLASMA;
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use PLASMA.mips_instruction_set.ALL;
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use PLASMA.plasma_pack.ALL;
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entity plasma_datapath_MIPSI_FPU is
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generic(
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core_idx : natural := 0;
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SIM_FLAG : string := "ON";
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DEBUG_FLAG : string := "OF"
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);
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port(
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control : in t_main_control;
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-- input control mux and registers
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reg_addr : in t_reg_addr;
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fpu_reg_addr : in t_reg_addr;
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mux_ctrl : in t_plasma_mux_ctrl;
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mux_fpu : in t_plasma_mux_fpu;
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stall_src : in t_stall_source;
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-- output feedback signals
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comp_out : out std_logic;
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fpu_cc : out std_logic;
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unit_busy : out t_unit_busy;
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-- operation units control
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unit_ctrl : in t_plasma_subunits_ctrl;
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fpu_ctrl : in t_fpu_ctrl;
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-- data
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instr_addr : out t_plasma_word;
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data_addr : out t_plasma_word;
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instr_in : in t_plasma_word;
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data_from_mem : in t_plasma_word;
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data_to_mem : out t_plasma_word
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);
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end entity plasma_datapath_MIPSI_FPU;
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architecture structure_plasma_datapath_MIPSI_FPU of plasma_datapath_MIPSI_FPU is
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-- ___ ____ ____ ____ ____ ____ _ _ ____ ____ _ _ _ _ ___ ____ ____
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-- |__] |__/ | | | __ |__/ |__| |\/| | | | | | |\ | | |___ |__/
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-- | | \ |__| |__] | \ | | | | |___ |__| |__| | \| | |___ | \
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signal pc_new_value : t_plasma_word; -- next pc value
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signal pc_out_inc : t_plasma_word; -- pc + 4
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signal pc_out_branch : t_plasma_word; -- pc + 4 + (imm16 << 2)
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-- ____ ____ ____ _ ____ ___ ____ ____ ___ ____ _ _ _ _
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-- |__/ |___ | __ | [__ | |___ |__/ |__] |__| |\ | |_/
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-- | \ |___ |__] | ___] | |___ | \ |__] | | | \| | \_
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signal regular_rd : t_mips_reg_addr;
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signal reg_bank_a : t_plasma_word; -- rs
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signal reg_bank_b : t_plasma_word; -- rt
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-- _ _ _ _ _ _ _ _ _ _ _
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-- | |\/| |\/| |\/| | | \/
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-- | | | | | | | |__| _/\_
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alias i_shamt : t_mips_shamt is instr_in(10 downto 6);
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alias i_imm : t_mips_imm16 is instr_in(15 downto 0);
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alias i_imm_long : t_mips_imm26 is instr_in(25 downto 0);
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signal i_imm_sign : t_mips_imm16;
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signal i_imm_branch : std_logic_vector(31 downto 18);
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constant ZERO_SHAMT : std_logic_vector(31 downto 5) := (others => '0');
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constant ZERO_IMM16 : std_logic_vector(15 downto 0) := (others => '0');
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constant ZERO_IMM26 : std_logic_vector(31 downto 28) := (others => '0');
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-- _ _ _ ___ _ _ ___ _ _ _ _ _ _ ____ ____
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-- | |\ | |__] | | | |\/| | | \/ |___ [__
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-- | | \| | |__| | | | |__| _/\_ |___ ___]
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signal src_a_in : t_plasma_word;
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signal i_src_b_in : t_plasma_word;
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signal src_b_in : t_plasma_word;
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signal imm_in : t_plasma_word;
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signal mem_data_in : t_plasma_word;
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signal data_from_fpu : t_plasma_word;
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-- ____ _ _ ____ ___ ____ ____ ____ ____ ____ ____ ____
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-- |___ \/ [__ | |__| | __ |___ |__/ |___ | __ [__
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-- |___ _/\_ ___] | | | |__] |___ | \ |___ |__] ___]
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signal reg_src_a_in : t_plasma_word;
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signal reg_src_b_in : t_plasma_word;
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signal reg_imm_in : t_plasma_word;
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signal reg_mem_data_in : t_plasma_word;
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-- ____ _ _ ___ ___ _ _ ___ _ _ _ _ _ _
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-- | | | | | |__] | | | |\/| | | \/
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-- |__| |__| | | |__| | | | |__| _/\_
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signal alu_out : t_plasma_word;
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signal shift_out : t_plasma_word;
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signal mult_out : t_plasma_word;
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signal op_data_out : t_plasma_word;
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-- _ _ ____ _ _ ____ ___ ____ ____ ____ ____ ____ ____
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-- |\/| |___ |\/| [__ | |__| | __ |___ |__/ |___ | __
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-- | | |___ | | ___] | | | |__] |___ | \ |___ |__]
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signal reg_mem_result : t_plasma_word;
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signal reg_mem_to_memory : t_plasma_word;
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signal mem_data_out : t_plasma_word;
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-- _ _ _ ___ ____ ___ ____ ____ ____ ____ ____ ____
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-- | | | |__] [__ | |__| | __ |___ |__/ |___ | __
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-- |_|_| |__] ___] | | | |__] |___ | \ |___ |__]
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signal reg_bank_in : t_plasma_word;
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begin ---------- BEGIN -------------------- BEGIN --------------------- BEGIN -------------------
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-- ----------------------------------------------------------------------------------------------
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-- _____ _____ ____ _____ _____ __ __ _____ ____ _ _ _ _ _______ ______ _____
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-- | __ \| __ \ / __ \ / ____| __ \ /\ | \/ | / ____/ __ \| | | | \ | |__ __| ____| __ \
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-- | |__) | |__) | | | | | __| |__) | / \ | \ / | | | | | | | | | | \| | | | | |__ | |__) |
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-- | ___/| _ /| | | | | |_ | _ / / /\ \ | |\/| | | | | | | | | | | . ` | | | | __| | _ /
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-- | | | | \ \| |__| | |__| | | \ \ / ____ \| | | | | |___| |__| | |__| | |\ | | | | |____| | \ \
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-- |_| |_| \_\\____/ \_____|_| \_\/_/ \_\_| |_| \_____\____/ \____/|_| \_| |_| |______|_| \_\
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-- ----------------------------------------------------------------------------------------------
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--
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-- PC UNIT
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--
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u1_pc: plasma_pc
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PORT MAP(
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control => control,
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stall => stall_src.pc,
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pc_imm_in => reg_imm_in,
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pc_new_value => pc_new_value,
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pc_out.pc_out_inc => pc_out_inc,
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pc_out.pc_out_branch => pc_out_branch,
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pc_out.pc_out => instr_addr
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);
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-- ----------------------------------------------------------------------------------------------
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-- _____ ______ _____ _____ _____ _______ ______ _____ ____ _ _ _ __
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-- | __ \| ____/ ____|_ _|/ ____|__ __| ____| __ \ | _ \ /\ | \ | | |/ /
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-- | |__) | |__ | | __ | | | (___ | | | |__ | |__) | | |_) | / \ | \| | ' /
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-- | _ /| __|| | |_ | | | \___ \ | | | __| | _ / | _ < / /\ \ | . ` | <
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-- | | \ \| |___| |__| |_| |_ ____) | | | | |____| | \ \ | |_) / ____ \| |\ | . \
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-- |_| \_\______\_____|_____|_____/ |_| |______|_| \_\ |____/_/ \_\_| \_|_|\_\
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-- ----------------------------------------------------------------------------------------------
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--
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-- REGISTER BANK UNIT
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--
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u2_reg_bank: plasma_reg_bank
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GENERIC MAP(
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core_idx => core_idx,
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DEBUG_FLAG => DEBUG_FLAG
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)
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PORT MAP(
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control => control,
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reg_addr => reg_addr,
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reg_dest_new => reg_bank_in,
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reg_source_out => reg_bank_a,
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reg_target_out => reg_bank_b
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);
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-- ----------------------------------------------------------------------------------------------
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-- ----------------------------------------------------------------------------------------------
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-- ###### ####### ##### ####### ###### ####### ##### ####### # ##### #######
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-- # # # # # # # # # # # # # # # # # #
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-- # # # # # # # # # # # # # # #
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-- # # ##### # # # # # ##### ##### # # # # #### #####
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-- # # # # # # # # # # # ####### # # #
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-- # # # # # # # # # # # # # # # # # #
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-- ###### ####### ##### ####### ###### ####### ##### # # # ##### #######
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-- ----------------------------------------------------------------------------------------------
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-- ----------------------------------------------------------------------------------------------
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-- _____ _ _ _____ _ _ _______ __ __ _ ___ ________ _____
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-- |_ _| \ | | __ \| | | |__ __| | \/ | | | \ \ / / ____|/ ____|
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-- | | | \| | |__) | | | | | | | \ / | | | |\ V /| |__ | (___
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-- | | | . ` | ___/| | | | | | | |\/| | | | | > < | __| \___ \
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-- _| |_| |\ | | | |__| | | | | | | | |__| |/ . \| |____ ____) |
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-- |_____|_| \_|_| \____/ |_| |_| |_|\____//_/ \_\______|_____/
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-- ----------------------------------------------------------------------------------------------
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--
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-- IMMEDIATE VALUE MUX
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--
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i_imm_sign <= (others => i_imm(15));
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i_imm_branch <= (others => i_imm(15));
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with mux_ctrl.src_imm select
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imm_in <= ZERO_IMM16 & i_imm when IMM_UNSIGN,
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i_imm & ZERO_IMM16 when IMM_HIGH,
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ZERO_SHAMT & i_shamt when IMM_SHAMT,
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i_imm_branch & i_imm & b"00" when IMM_BRANCH,
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ZERO_IMM26 & i_imm_long & b"00" when IMM_JUMP,
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i_imm_sign & i_imm when others;
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--
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-- SOURCE A MUX
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--
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with mux_ctrl.src_a select
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src_a_in <= op_data_out when SRC_OP_OUT,
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mem_data_out when SRC_MEM_OUT,
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reg_bank_in when SRC_WB_OUT,
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reg_bank_a when others;
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--
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-- SOURCE B MUX
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--
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with mux_ctrl.src_b select
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i_src_b_in <= op_data_out when SRC_OP_OUT,
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mem_data_out when SRC_MEM_OUT,
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reg_bank_in when SRC_WB_OUT,
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reg_bank_b when others;
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--
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-- IMMEDIATE SWITCH
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--
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with mux_ctrl.src_b_imm select
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src_b_in <= imm_in when B_IMM_ON,
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i_src_b_in when others;
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--
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-- MEMORY INPUT
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--
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with mux_fpu.cop select
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mem_data_in <= data_from_fpu when COP_SELECT_COP1,
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i_src_b_in when others;
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-- ----------------------------------------------------------------------------------------------
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-- ----------------------------------------------------------------------------------------------
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-- ####### # # ####### ##### # # ####### ####### ##### ####### # ##### #######
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-- # # # # # # # # # # # # # # # # # #
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-- # # # # # # # # # # # # # # #
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-- ##### # ##### # # # # ##### ##### # # # # #### #####
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-- # # # # # # # # # # # ####### # # #
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-- # # # # # # # # # # # # # # # # # #
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-- ####### # # ####### ##### ##### # ####### ##### # # # ##### #######
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-- ----------------------------------------------------------------------------------------------
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-- ----------------------------------------------------------------------------------------------
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-- ________ __ _____ _______ _____ ______ _____ ______ _____ _____
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-- | ____\ \ / / / ____|__ __|/\ / ____| ____| | __ \| ____/ ____|/ ____|
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-- | |__ \ V / | (___ | | / \ | | __| |__ | |__) | |__ | | __| (___
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-- | __| > < \___ \ | | / /\ \| | |_ | __| | _ /| __|| | |_ |\___ \
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-- | |____ / . \ ____) | | |/ ____ \ |__| | |____ | | \ \| |___| |__| |____) |
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-- |______/_/ \_\ |_____/ |_/_/ \_\_____|______| |_| \_\______\_____|_____/
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-- ----------------------------------------------------------------------------------------------
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ex_stage_registers:
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process( control.clk )
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begin
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if rising_edge( control.clk ) then
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if control.rst = '1' then
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reg_src_a_in <= PLASMA_ZERO_WORD;
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reg_src_b_in <= PLASMA_ZERO_WORD;
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reg_imm_in <= PLASMA_ZERO_WORD;
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reg_mem_data_in <= PLASMA_ZERO_WORD;
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else
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if stall_src.pc = '0' then
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reg_src_a_in <= src_a_in;
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reg_src_b_in <= src_b_in;
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reg_imm_in <= imm_in;
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reg_mem_data_in <= mem_data_in;
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end if;
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end if;
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end if;
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end process;
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-- ----------------------------------------------------------------------------------------------
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-- ____ _____ ______ _____ _______ _____ ____ _ _ _ _ _ _ _____ _______ _____
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-- / __ \| __ \| ____| __ \ /\|__ __|_ _/ __ \| \ | | | | | | \ | |_ _|__ __/ ____|
|
304 |
|
|
-- | | | | |__) | |__ | |__) | / \ | | | || | | | \| | | | | | \| | | | | | | (___
|
305 |
|
|
-- | | | | ___/| __| | _ / / /\ \ | | | || | | | . ` | | | | | . ` | | | | | \___ \
|
306 |
|
|
-- | |__| | | | |____| | \ \ / ____ \| | _| || |__| | |\ | | |__| | |\ |_| |_ | | ____) |
|
307 |
|
|
-- \____/|_| |______|_| \_\/_/ \_\_| |_____\____/|_| \_| \____/|_| \_|_____| |_| |_____/
|
308 |
|
|
-- ----------------------------------------------------------------------------------------------
|
309 |
|
|
-- ____ _ _ _ _ _ _ ____ ___ _ ____ _ _
|
310 |
|
|
-- [__ | |\/| | | | |__| | | | | |\ |
|
311 |
|
|
-- ___] | | | |__| |___ | | | | |__| | \|
|
312 |
|
|
--synthesis translate_off
|
313 |
|
|
SIM: if SIM_FLAG = "ON" generate
|
314 |
|
|
--
|
315 |
|
|
-- ALU
|
316 |
|
|
--
|
317 |
|
|
u3_alu: entity PLASMA.plasma_alu(sim_alu)
|
318 |
|
|
PORT MAP(
|
319 |
|
|
alu_a_in => reg_src_a_in, alu_b_in => reg_src_b_in,
|
320 |
|
|
alu_func => unit_ctrl.alu_func,
|
321 |
|
|
alu_out => alu_out
|
322 |
|
|
);
|
323 |
|
|
|
324 |
|
|
--
|
325 |
|
|
-- SHIFTER
|
326 |
|
|
--
|
327 |
|
|
u4_shifter: entity PLASMA.plasma_shifter(sim_shifter)
|
328 |
|
|
PORT MAP(
|
329 |
|
|
shift_in => reg_src_a_in, shift_amount => reg_src_b_in(4 downto 0),
|
330 |
|
|
shift_func => unit_ctrl.shift_func,
|
331 |
|
|
shift_out => shift_out
|
332 |
|
|
);
|
333 |
|
|
|
334 |
|
|
--
|
335 |
|
|
-- MULTIPLICATOR
|
336 |
|
|
--
|
337 |
|
|
u5_mult: entity PLASMA.plasma_mult(sim_mult)
|
338 |
|
|
PORT MAP(
|
339 |
|
|
control => control,
|
340 |
|
|
mult_a_in => reg_src_a_in, mult_b_in => reg_src_b_in,
|
341 |
|
|
mult_func => unit_ctrl.mult_func, mult_busy => unit_busy.mult,
|
342 |
|
|
mult_out => mult_out
|
343 |
|
|
);
|
344 |
|
|
|
345 |
|
|
--
|
346 |
|
|
-- COMPARATOR
|
347 |
|
|
--
|
348 |
|
|
u6_comp: entity PLASMA.plasma_comparator(structure_comparator)
|
349 |
|
|
PORT MAP(
|
350 |
|
|
comp_a_in => reg_src_a_in, comp_b_in => reg_src_b_in,
|
351 |
|
|
comp_func => unit_ctrl.comp_func,
|
352 |
|
|
comp_out => comp_out
|
353 |
|
|
);
|
354 |
|
|
end generate;
|
355 |
|
|
|
356 |
|
|
--
|
357 |
|
|
-- FPU
|
358 |
|
|
--
|
359 |
|
|
u7_fpu: entity PLASMA.plasma_fpu(behav_plasma_fpu)
|
360 |
|
|
GENERIC MAP( DEBUG_FLAG => DEBUG_FLAG)
|
361 |
|
|
PORT MAP(
|
362 |
|
|
control => control,
|
363 |
|
|
|
364 |
|
|
fpu_reg_addr => fpu_reg_addr, fpu_ctrl => fpu_ctrl,
|
365 |
|
|
|
366 |
|
|
busy => unit_busy.fpu, cc_out => fpu_cc,
|
367 |
|
|
|
368 |
|
|
fpu_id_sel => mux_fpu.fpu_id, fpu_mem_sel => mux_fpu.fpu_mem,
|
369 |
|
|
|
370 |
|
|
data_to_fpu => i_src_b_in,
|
371 |
|
|
data_from_fpu => data_from_fpu,
|
372 |
|
|
data_to_fpu_mem => data_from_mem
|
373 |
|
|
);
|
374 |
|
|
--synthesis translate_on
|
375 |
|
|
|
376 |
|
|
|
377 |
|
|
-- ____ ___ ____ ____
|
378 |
|
|
-- |___ |__] | __ |__|
|
379 |
|
|
-- | | |__] | |
|
380 |
|
|
FPGA: if SIM_FLAG = "OF" generate
|
381 |
|
|
--
|
382 |
|
|
-- ALU
|
383 |
|
|
--
|
384 |
|
|
u3_alu: entity PLASMA.plasma_alu(FPGA_alu)
|
385 |
|
|
PORT MAP(
|
386 |
|
|
alu_a_in => reg_src_a_in, alu_b_in => reg_src_b_in,
|
387 |
|
|
alu_func => unit_ctrl.alu_func,
|
388 |
|
|
alu_out => alu_out
|
389 |
|
|
);
|
390 |
|
|
|
391 |
|
|
--
|
392 |
|
|
-- SHIFTER
|
393 |
|
|
--
|
394 |
|
|
u4_shifter: entity PLASMA.plasma_shifter(FPGA_shifter)
|
395 |
|
|
PORT MAP(
|
396 |
|
|
shift_in => reg_src_a_in, shift_amount => reg_src_b_in(4 downto 0),
|
397 |
|
|
shift_func => unit_ctrl.shift_func,
|
398 |
|
|
shift_out => shift_out
|
399 |
|
|
);
|
400 |
|
|
|
401 |
|
|
--
|
402 |
|
|
-- MULTIPLICATOR
|
403 |
|
|
--
|
404 |
|
|
u5_mult: entity PLASMA.plasma_mult(FPGA_mult)
|
405 |
|
|
PORT MAP(
|
406 |
|
|
control => control,
|
407 |
|
|
mult_a_in => reg_src_a_in, mult_b_in => reg_src_b_in,
|
408 |
|
|
mult_func => unit_ctrl.mult_func, mult_busy => unit_busy.mult,
|
409 |
|
|
mult_out => mult_out
|
410 |
|
|
);
|
411 |
|
|
|
412 |
|
|
--
|
413 |
|
|
-- COMPARATOR
|
414 |
|
|
--
|
415 |
|
|
u6_comp: entity PLASMA.plasma_comparator(structure_comparator)
|
416 |
|
|
PORT MAP(
|
417 |
|
|
comp_a_in => reg_src_a_in, comp_b_in => reg_src_b_in,
|
418 |
|
|
comp_func => unit_ctrl.comp_func,
|
419 |
|
|
comp_out => comp_out
|
420 |
|
|
);
|
421 |
|
|
end generate;
|
422 |
|
|
|
423 |
|
|
|
424 |
|
|
|
425 |
|
|
-- ____ _ _ _______ _____ _ _ _______ __ __ _ ___ __
|
426 |
|
|
-- / __ \| | | |__ __| __ \| | | |__ __| | \/ | | | \ \ / /
|
427 |
|
|
-- | | | | | | | | | | |__) | | | | | | | \ / | | | |\ V /
|
428 |
|
|
-- | | | | | | | | | | ___/| | | | | | | |\/| | | | | > <
|
429 |
|
|
-- | |__| | |__| | | | | | | |__| | | | | | | | |__| |/ . \
|
430 |
|
|
-- \____/ \____/ |_| |_| \____/ |_| |_| |_|\____//_/ \_\
|
431 |
|
|
--
|
432 |
|
|
-- OUTPUT MUX
|
433 |
|
|
--
|
434 |
|
|
with mux_ctrl.src_out select
|
435 |
|
|
op_data_out <= pc_out_inc when SRC_OUT_PC,
|
436 |
|
|
shift_out when SRC_OUT_SHIFT,
|
437 |
|
|
mult_out when SRC_OUT_MULT,
|
438 |
|
|
reg_mem_data_in when SRC_OUT_MEM_DATA,
|
439 |
|
|
alu_out when others;
|
440 |
|
|
|
441 |
|
|
--
|
442 |
|
|
-- PC VALUE MUX
|
443 |
|
|
--
|
444 |
|
|
with unit_ctrl.pc_func select
|
445 |
|
|
pc_new_value <= reg_imm_in when PLASMA_PC_IMM,
|
446 |
|
|
reg_src_a_in when PLASMA_PC_REG,
|
447 |
|
|
pc_out_branch when PLASMA_PC_BRANCH,
|
448 |
|
|
pc_out_inc when others;
|
449 |
|
|
|
450 |
|
|
-- ----------------------------------------------------------------------------------------------
|
451 |
|
|
-- ----------------------------------------------------------------------------------------------
|
452 |
|
|
-- # # ####### # # ####### ###### # # ##### ####### # ##### #######
|
453 |
|
|
-- ## ## # ## ## # # # # # # # # # # # # # #
|
454 |
|
|
-- # # # # # # # # # # # # # # # # # # # # #
|
455 |
|
|
-- # # # ##### # # # # # ###### # ##### # # # # #### #####
|
456 |
|
|
-- # # # # # # # # # # # # ####### # # #
|
457 |
|
|
-- # # # # # # # # # # # # # # # # # #
|
458 |
|
|
-- # # ####### # # ####### # # # ##### # # # ##### #######
|
459 |
|
|
-- ----------------------------------------------------------------------------------------------
|
460 |
|
|
--
|
461 |
|
|
-- MEMORY STAGE RESTIERS
|
462 |
|
|
--
|
463 |
|
|
mem_stage_register:
|
464 |
|
|
process( control.clk )
|
465 |
|
|
begin
|
466 |
|
|
if rising_edge( control.clk ) then
|
467 |
|
|
if control.rst = '1' then
|
468 |
|
|
reg_mem_result <= PLASMA_ZERO_WORD;
|
469 |
|
|
reg_mem_to_memory <= PLASMA_ZERO_WORD;
|
470 |
|
|
else
|
471 |
|
|
if (stall_src.data = '0') and
|
472 |
|
|
(stall_src.unit = '0') then
|
473 |
|
|
reg_mem_result <= op_data_out;
|
474 |
|
|
reg_mem_to_memory <= reg_mem_data_in;
|
475 |
|
|
end if;
|
476 |
|
|
end if;
|
477 |
|
|
end if;
|
478 |
|
|
end process;
|
479 |
|
|
|
480 |
|
|
--
|
481 |
|
|
-- MEMORY ACCESS OUTPUT
|
482 |
|
|
--
|
483 |
|
|
data_addr <= reg_mem_result; -- memory access address
|
484 |
|
|
data_to_mem <= reg_mem_to_memory; -- memory access data
|
485 |
|
|
|
486 |
|
|
--
|
487 |
|
|
-- MEMORY STAGE MUX
|
488 |
|
|
--
|
489 |
|
|
with mux_ctrl.wb select
|
490 |
|
|
mem_data_out <= data_from_mem when WB_MEMORY,
|
491 |
|
|
reg_mem_result when others;
|
492 |
|
|
|
493 |
|
|
-- ----------------------------------------------------------------------------------------------
|
494 |
|
|
-- ----------------------------------------------------------------------------------------------
|
495 |
|
|
-- # # ###### ### ####### ####### ###### # ##### # # ##### ####### # ##### #######
|
496 |
|
|
-- # # # # # # # # # # # # # # # # # # # # # # # #
|
497 |
|
|
-- # # # # # # # # # # # # # # # # # # # # #
|
498 |
|
|
-- # # # ###### # # ##### ###### # # # ### ##### # # # # #### #####
|
499 |
|
|
-- # # # # # # # # # # ####### # # # # # ####### # # #
|
500 |
|
|
-- # # # # # # # # # # # # # # # # # # # # # # # #
|
501 |
|
|
-- ## ## # # ### # ####### ###### # # ##### # # ##### # # # ##### #######
|
502 |
|
|
-- ----------------------------------------------------------------------------------------------
|
503 |
|
|
--
|
504 |
|
|
-- WRITE BACK STAGE REGISTER
|
505 |
|
|
--
|
506 |
|
|
wb_stage_register:
|
507 |
|
|
process( control.clk )
|
508 |
|
|
begin
|
509 |
|
|
if rising_edge( control.clk ) then
|
510 |
|
|
if control.rst = '1' then
|
511 |
|
|
reg_bank_in <= PLASMA_ZERO_WORD;
|
512 |
|
|
else
|
513 |
|
|
if (stall_src.data = '0') then
|
514 |
|
|
reg_bank_in <= mem_data_out;
|
515 |
|
|
end if;
|
516 |
|
|
end if;
|
517 |
|
|
end if;
|
518 |
|
|
end process;
|
519 |
|
|
|
520 |
|
|
end architecture structure_plasma_datapath_MIPSI_FPU;
|
521 |
|
|
|