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__alexs__ |
-- --------------------------------------------------------------------------
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-- >>>>>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<<
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-- --------------------------------------------------------------------------
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-- TITLE: MIPS Instruction Set Binary
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-- AUTHOR: Alex Schoenberger (Alex.Schoenberger@ies.tu-darmstadt.de)
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-- COMMENT: This project is based on Plasma CPU core by Steve Rhoads
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--
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-- www.ies.tu-darmstadt.de
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-- TU Darmstadt
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-- Institute for Integrated Systems
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-- Merckstr. 25
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--
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-- 64283 Darmstadt - GERMANY
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-- --------------------------------------------------------------------------
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-- PROJECT: Plasma CPU core with FPU
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-- FILENAME: mips_instruction_set.vhd
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-- --------------------------------------------------------------------------
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-- COPYRIGHT:
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-- This project is distributed by GPLv2.0
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-- Software placed into the public domain by the author.
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-- Software 'as is' without warranty. Author liable for nothing.
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-- --------------------------------------------------------------------------
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-- DESCRIPTION:
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-- selected subset of MIPS instruction set binary
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----------------------------------------------------------------------------
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-- Revision History
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-- --------------------------------------------------------------------------
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-- Revision Date Author CHANGES
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-- 1.0 4/2014 AS initial
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-- --------------------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.ALL;
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package mips_instruction_set is
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-- --------------------------------------------------------------------------------------------------------
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-- _____ _ _ _____ _______ _____ _ _ _____ _______ _____ ____ _ _ _____ ______ _______
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-- |_ _| \ | |/ ____|__ __| __ \| | | |/ ____|__ __|_ _/ __ \| \ | | / ____| ____|__ __|
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-- | | | \| | (___ | | | |__) | | | | | | | | || | | | \| | | (___ | |__ | |
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-- | | | . ` |\___ \ | | | _ /| | | | | | | | || | | | . ` | \___ \| __| | |
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-- _| |_| |\ |____) | | | | | \ \| |__| | |____ | | _| || |__| | |\ | ____) | |____ | |
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-- |_____|_| \_|_____/ |_| |_| \_\\____/ \_____| |_| |_____\____/|_| \_| |_____/|______| |_|
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-- --------------------------------------------------------------------------------------------------------
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-- _ _ _ ____ ___ ____ _ _ ____ ___ _ ____ _ _ ____ ____ _ _ ___ ____ _ _ ____ _ _ ___ ____
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-- | |\ | [__ | |__/ | | | | | | | |\ | | | | |\/| |__] | | |\ | |___ |\ | | [__
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-- | | \| ___] | | \ |__| |___ | | |__| | \| |___ |__| | | | |__| | \| |___ | \| | ___]
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--
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subtype t_mips_opcode is std_logic_vector( 5 downto 0); -- operation code
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subtype t_mips_format is std_logic_vector( 4 downto 0); -- format code
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subtype t_mips_function is std_logic_vector( 5 downto 0); -- function code
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subtype t_mips_reg_addr is std_logic_vector( 4 downto 0); -- register address
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subtype t_mips_shamt is std_logic_vector( 4 downto 0); -- shift amount value
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subtype t_mips_imm11 is std_logic_vector(10 downto 0); -- immediate value for coprocessor
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subtype t_mips_imm16 is std_logic_vector(15 downto 0); -- immediate value for calculation/memory
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subtype t_mips_imm26 is std_logic_vector(25 downto 0); -- immmediate value for jumps
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subtype t_mips_fmt is std_logic_vector( 4 downto 0); -- format for coprocessor
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subtype t_mips_cond is std_logic_vector( 3 downto 0); -- FPU compare condition
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subtype t_mips_cc is std_logic_vector( 2 downto 0); -- FPU condition code address
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subtype t_mips_z_branch is std_logic_vector( 1 downto 0); -- FPU branch coding
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subtype t_mips_i_ctrl_bit is std_logic;
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-- --------------------------------------------------------------------------------------
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-- ____ ____ _ _ ____ ___ ____ ___ _ _ ___ ____
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-- | | | |\ | [__ | |__| | |\ | | [__
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-- |___ |__| | \| ___] | | | | | \| | ___]
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--
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-- SPECIAL REGISTER
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--
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constant MIPS_R_ZERO : t_mips_reg_addr := b"0_0000"; -- zero value register
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constant MIPS_R_RA : t_mips_reg_addr := b"1_1111"; -- return value register address
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-- --------------------------------------------------------------------------------------
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-- ____ _ _ _ _ ____ ___ _ ____ _ _ ____ _ ____ _ _ ____ ____ ___ _ _ _ ____
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-- |___ | | |\ | | | | | | |\ | |__| | |___ |\ | | | | | \ | |\ | | __
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-- | |__| | \| |___ | | |__| | \| | | |___ |___ | \| |___ |__| |__/ | | \| |__]
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-- --------------------------------------------------------------------------------------
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-- ____ ____ ____ ____ ____ ____ _ ____ ___ ____ ____ ____ ____ ____ _ _ ____ ___
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-- |___ | | |__/ |__/ |___ | __ | [__ | |___ |__/ |___ | | |__/ |\/| |__| |
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-- | |__| | \ | \ |___ |__] | ___] | |___ | \ | |__| | \ | | | | |
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--
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-- opcode(6) & rs(5) & rt(5) & rd(5) & shamt(5) & funct(6)
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--
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constant MIPS_OPCODE_REG : t_mips_opcode := b"00_0000";
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--
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-- shifter operations
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constant MIPS_FUNC_SLL : t_mips_function := b"00_0000"; -- rd = rt << sa
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constant MIPS_FUNC_SRL : t_mips_function := b"00_0010"; -- rd = rt >> sa
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constant MIPS_FUNC_SRA : t_mips_function := b"00_0011"; -- rd = signed(rt) >> sa
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constant MIPS_FUNC_SLLV : t_mips_function := b"00_0100"; -- rd = rt << rs
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constant MIPS_FUNC_SRLV : t_mips_function := b"00_0110"; -- rd = rt >> rs
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constant MIPS_FUNC_SRAV : t_mips_function := b"00_0111"; -- rd = signed(rt) >> rs
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-- jump register
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constant MIPS_FUNC_JR : t_mips_function := b"00_1000"; -- pc = rs
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constant MIPS_FUNC_JALR : t_mips_function := b"00_1001"; -- pc = rs; rd = pc
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-- conditional move
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constant MIPS_FUNC_MOVZ : t_mips_function := b"00_1010"; -- if (rt = 0) rd = rs
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constant MIPS_FUNC_MOVN : t_mips_function := b"00_1011"; -- if (rt != 0) rd = rs
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-- syscall and break
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constant MIPS_FUNC_SYSCALL : t_mips_function := b"00_1100"; -- epc = pc; pc = 0x3c
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constant MIPS_FUNC_BREAK : t_mips_function := b"00_1101"; -- epc = pc; pc = 0x3c
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-- multiplication register moving
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constant MIPS_FUNC_MFHI : t_mips_function := b"01_0000"; -- rd = HI
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constant MIPS_FUNC_MTHI : t_mips_function := b"01_0001"; -- HI = rs
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constant MIPS_FUNC_MFLO : t_mips_function := b"01_0010"; -- rd = LO
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constant MIPS_FUNC_MTLO : t_mips_function := b"01_0011"; -- LO = rs
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-- multiplication/division
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constant MIPS_FUNC_MULT : t_mips_function := b"01_1000"; -- HI,LO = rs * rt
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constant MIPS_FUNC_MULTU : t_mips_function := b"01_1001"; -- HI,LO = signed(rs) * signed(rt)
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constant MIPS_FUNC_DIV : t_mips_function := b"01_1010"; -- HI = rs % rt; LO = rs / rt
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constant MIPS_FUNC_DIVU : t_mips_function := b"01_1011"; -- HI = rs % rt; LO = signed(rs) / sigend(rt)
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-- addition/substraction
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constant MIPS_FUNC_ADD : t_mips_function := b"10_0000"; -- rd = rs + rt
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constant MIPS_FUNC_ADDU : t_mips_function := b"10_0001"; -- rd = unsigned(rs) + unsigned(rt)
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constant MIPS_FUNC_SUB : t_mips_function := b"10_0010"; -- rd = rs - rt
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constant MIPS_FUNC_SUBU : t_mips_function := b"10_0011"; -- rd = unsigned(rs) - unsigned(rt)
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-- logic manipulation
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constant MIPS_FUNC_AND : t_mips_function := b"10_0100"; -- rd = rs and rt
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constant MIPS_FUNC_OR : t_mips_function := b"10_0101"; -- rd = rs or rt
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constant MIPS_FUNC_XOR : t_mips_function := b"10_0110"; -- rd = rs xor rt
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constant MIPS_FUNC_NOR : t_mips_function := b"10_0111"; -- rd = rs nor rt
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-- comparison
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constant MIPS_FUNC_SLT : t_mips_function := b"10_1010"; -- rd = rs < rt
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constant MIPS_FUNC_SLTU : t_mips_function := b"10_1011"; -- rd = unsigned(rs) < unsigend(rt)
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-- ____ ___ ____ ____ _ ____ _ _ _
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-- [__ |__] |___ | | |__| | | |
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-- ___] | |___ |___ | | | |___ | |
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--
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-- opcode(6) & rs(5) & rt(5) & rd(5) & shamt(5) & funct(6)
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--
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constant MIPS_OPCODE_SPECIAL2 : t_mips_opcode := b"01_1100"; -- special2 insructions
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constant MIPS_FUNC_MADD : t_mips_function := b"00_0000"; --(HI,LO) = (HI,LO) + (rs*rt)
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constant MIPS_FUNC_MADDU : t_mips_function := b"00_0001"; --(HI,LO) = (HI,LO) + unsigned(rs*rt)
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constant MIPS_FUNC_MUL : t_mips_function := b"00_0010"; -- rd = rs * rt;
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constant MIPS_FUNC_MSUB : t_mips_function := b"00_0100"; -- (HI,LO) = (HI,LO) - (rs*rt)
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constant MIPS_FUNC_MSUBU : t_mips_function := b"00_0101"; -- (HI,LO) = (HI,LO) - unsigned(rs*rt)
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-- ____ ___ ____ ____ _ ____ _ _ _ _
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-- [__ |__] |___ | | |__| | | | |
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-- ___] | |___ |___ | | | |___ | | |
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--
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-- opcode(6) & rs(5) & rt(5) & rd(5) & shamt(5) & funct(6)
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--
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constant MIPS_OPCODE_SPECIAL3 : t_mips_opcode := b"01_1111"; -- special3 instructions
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constant MIPS_FUNC_INS : t_mips_function := b"00_0100"; -- insert bit field
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constant MIPS_FUNC_EXT : t_mips_function := b"00_0000"; -- extract bit field
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constant MIPS_FUNC_BSHFL : t_mips_function := b"10_0000";
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constant MIPS_FUNC_BSHFL_SEB : t_mips_shamt := b"1_0000"; -- sign-extend byte
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constant MIPS_FUNC_BSHFL_SEH : t_mips_shamt := b"1_1000"; -- sign-extend halfword
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constant MIPS_FUNC_BSHFL_WSBH : t_mips_shamt := b"1_0010"; -- Word Swap bytes Within Halfwords
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-- ____ ____ ____ _ _ ____
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-- | |__| | |__| |___
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-- |___ | | |___ | | |___
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constant MIPS_OPCODE_PREF : t_mips_opcode := b"11_0011"; -- prefetch data
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constant MIPS_OPCODE_CACHE : t_mips_opcode := b"10_1111"; -- update cache
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-- ____ ____ ____ _ _ _ _ _
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-- |__/ |___ | __ | |\/| |\/|
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-- | \ |___ |__] | | | | |
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--
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-- 00_0001 & rs(5) & func & imm16
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--
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constant MIPS_OPCODE_REGIMM : t_mips_opcode := b"00_0001"; -- REGIMM instruction class
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constant MIPS_OPCODE_BLTZ : t_mips_reg_addr := b"0_0000"; -- if(rs < 0) pc = imm16 << 2
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constant MIPS_OPCODE_BGEZ : t_mips_reg_addr := b"0_0001"; -- if(rs >= 0) pc = imm16 << 2
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constant MIPS_OPCODE_BLTZAL : t_mips_reg_addr := b"1_0000"; -- if(rs < 0) pc = imm16 << 2; r31 = pc
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constant MIPS_OPCODE_BGEZAL : t_mips_reg_addr := b"1_0001"; -- if(rs >= 0) pc = imm16 << 2; r31 = pc
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-- --------------------------------------------------------------------------------------
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-- _ _ _ _ _ ___ ____ ____ ____ _ _ ____ ___
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-- | | | |\/| |__] |___ | | |__/ |\/| |__| |
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-- _| |__| | | | | |__| | \ | | | | |
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-- --------------------------------------------------------------------------------------
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--
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-- opcode(6) & immediate(26)
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--
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constant MIPS_OPCODE_J : t_mips_opcode := b"00_0010"; -- pc = imm26 << 2
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constant MIPS_OPCODE_JAL : t_mips_opcode := b"00_0011"; -- pc = imm26 << 2; r31 = pc
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-- --------------------------------------------------------------------------------------
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-- _ _ _ _ _ ____ ___ _ ____ ___ ____ ____ ____ ____ _ _ ____ ___
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-- | |\/| |\/| |___ | \ | |__| | |___ |___ | | |__/ |\/| |__| |
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-- | | | | | |___ |__/ | | | | |___ | |__| | \ | | | | |
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-- --------------------------------------------------------------------------------------
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--
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-- opcode(6) & rs(5) & rt(5) & immediate(16)
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--
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-- ___ ____ ____ _ _ ____ _ _
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-- |__] |__/ |__| |\ | | |__|
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-- |__] | \ | | | \| |___ | |
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constant MIPS_OPCODE_BEQ : t_mips_opcode := b"00_0100"; -- if(rs == rt) pc = imm16 << 2
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constant MIPS_OPCODE_BNE : t_mips_opcode := b"00_0101"; -- if(rs != rt) pc = imm16 << 2
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constant MIPS_OPCODE_BLEZ : t_mips_opcode := b"00_0110"; -- if(rs <= 0) pc = imm16 << 2
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constant MIPS_OPCODE_BGTZ : t_mips_opcode := b"00_0111"; -- if(rs > 0) pc = imm16 << 2
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-- addition, comparison, logic
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constant MIPS_OPCODE_ADDI : t_mips_opcode := b"00_1000"; -- rt = rs + imm16
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constant MIPS_OPCODE_ADDIU : t_mips_opcode := b"00_1001"; -- rt = unsigned(rs) + imm16
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constant MIPS_OPCODE_SLTI : t_mips_opcode := b"00_1010"; -- rt = rs < imm16
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constant MIPS_OPCODE_SLTIU : t_mips_opcode := b"00_1011"; -- rt = unsigned(rs) < imm16
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constant MIPS_OPCODE_ANDI : t_mips_opcode := b"00_1100"; -- rt = rs and imm16
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constant MIPS_OPCODE_ORI : t_mips_opcode := b"00_1101"; -- rt = rs or imm16
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constant MIPS_OPCODE_XORI : t_mips_opcode := b"00_1110"; -- rt = rs xor imm16
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constant MIPS_OPCODE_LUI : t_mips_opcode := b"00_1111"; -- rt = imm16 << 16
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-- ____ ____ ___ ____ ____ ____ ____ ____ ____ ____ ____
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-- | | | |__] |__/ | | | |___ [__ [__ | | |__/
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-- |___ |__| | | \ |__| |___ |___ ___] ___] |__| | \
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--
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-- 01_00zz & fmt(5) & rt(5) & fs(5) & imm11
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--
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constant MIPS_OPCODE_COP0 : t_mips_opcode := b"01_0000"; -- coprocessor0 = interrupt
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constant MIPS_OPCODE_COP1 : t_mips_opcode := b"01_0001"; -- coprocessor1 = FPU
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constant MIPS_OPCODE_COP2 : t_mips_opcode := b"01_0010"; -- coprocessor2
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--
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-- 01_0000 & 0_1011 & rt(5) & 0_1100 & 0_0000 & func
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--
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constant MIPS_OPCODE_MFMC0 : t_mips_reg_addr := b"01_011"; -- disable/enable interrupts
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constant MIPS_FUNC_DI : t_mips_function := b"00_0000"; -- disable interrupts
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constant MIPS_FUNC_EI : t_mips_function := b"10_0000"; -- enable interrupts
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--
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-- 01_0000 & 1 & 000_0000_0000_0000_0000 & 01_1000
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--
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constant MIPS_FUNC_ERET : t_mips_function := b"01_1000"; -- exception return
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-- exchange between coprocessor and core
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constant MIPS_FMT_MFC : t_mips_fmt := b"0_0000"; -- rt = fs
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constant MIPS_FMT_CFC : t_mips_fmt := b"0_0010"; -- rt = cs
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constant MIPS_FMT_MTC : t_mips_fmt := b"0_0100"; -- fs = rt
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constant MIPS_FMT_CTC : t_mips_fmt := b"0_0110"; -- cs = rt
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-- branches
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constant MIPS_FMT_BRANCH : t_mips_fmt := b"0_1000"; -- FPU branch operation
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--
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-- FPU BRANCH OREPATIONS
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-- 01_0001(6) & 01000(5) & cc(3) & nd(1) & tf(1) & immediate(16)
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--
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constant MIPS_FUNC_FMT_BCZF : t_mips_z_branch := b"00"; -- branch if false
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constant MIPS_FUNC_FMT_BCZT : t_mips_z_branch := b"01"; -- branch if true
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constant MIPS_FUNC_FMT_BCZFL : t_mips_z_branch := b"10"; -- branch if false likely
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constant MIPS_FUNC_FMT_BCZTL : t_mips_z_branch := b"11"; -- branch if true likely
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-- operations
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constant MIPS_FMT_FLOAT_SINGLE: t_mips_fmt := b"1_0000"; -- operations with single precision
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constant MIPS_FMT_FLOAT_DOUBLE: t_mips_fmt := b"1_0001"; -- operations with double precision
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constant MIPS_FMT_FIXED_WORD : t_mips_fmt := b"1_0100"; -- operations with 32 bit words, fixed point
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constant MIPS_FMT_FIXED_LONG : t_mips_fmt := b"1_0101"; -- operations with 64 bit words, fixed point
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--
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-- OPERATIONS FOR FLOATIN OR FIXED POINT
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--
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-- ALU OPERATIONS
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-- 01_0001(6) & fmt(5) & ft(5) & fs(5) & fd(5) & func
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--
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constant MIPS_FUNC_FMT_ADD : t_mips_function := b"00_0000"; -- fd = fs + ft
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constant MIPS_FUNC_FMT_SUB : t_mips_function := b"00_0001"; -- fd = fs - ft
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constant MIPS_FUNC_FMT_MUL : t_mips_function := b"00_0010"; -- fd = fs * ft
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constant MIPS_FUNC_FMT_DIV : t_mips_function := b"00_0011"; -- fd = fs * ft
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constant MIPS_FUNC_FMT_SQRT : t_mips_function := b"00_0100"; -- fd = fs * ft
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constant MIPS_FUNC_FMT_ABS : t_mips_function := b"00_0101"; -- fd = fs * ft
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constant MIPS_FUNC_FMT_MOV : t_mips_function := b"00_0110"; -- fd = fs * ft
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constant MIPS_FUNC_FMT_NEG : t_mips_function := b"00_0111"; -- fd = fs * ft
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--
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-- CONVERT OPERATIONS
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-- 01_0001(6) & fmt(5) & 0_0000(5) & fs(5) & fd(5) & func
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--
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constant MIPS_FUNC_FMT_CVTS : t_mips_function := b"10_0000"; -- fd = convert_and_round(fs) to single precision
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constant MIPS_FUNC_FMT_CVTD : t_mips_function := b"10_0001"; -- fd = convert_and_round(fs) to double precision
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constant MIPS_FUNC_FMT_CVTW : t_mips_function := b"10_0100"; -- fd = convert_and_round(fs) to word
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--
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-- COMPARE OPERATIONS
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-- 01_0001(6) & fmt(5) & ft(5) & fs(5) & cc(3) & 00(2) & 11(2) & cond(4)
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--
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constant MIPS_FUNC_FMT_COND : t_mips_function := "11----"; -- general condition command
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constant MIPS_FUNC_FMT_C_F : t_mips_function := b"11_0000"; --
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constant MIPS_FUNC_FMT_C_UN : t_mips_function := b"11_0001"; --
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constant MIPS_FUNC_FMT_C_EQ : t_mips_function := b"11_0010"; --
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constant MIPS_FUNC_FMT_C_UEQ : t_mips_function := b"11_0011"; --
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constant MIPS_FUNC_FMT_C_OLT : t_mips_function := b"11_0100"; --
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constant MIPS_FUNC_FMT_C_ULT : t_mips_function := b"11_0101"; --
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constant MIPS_FUNC_FMT_C_OLE : t_mips_function := b"11_0110"; --
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307 |
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constant MIPS_FUNC_FMT_C_ULE : t_mips_function := b"11_0111"; --
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constant MIPS_FUNC_FMT_C_SF : t_mips_function := b"11_1000"; --
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constant MIPS_FUNC_FMT_C_NGLE : t_mips_function := b"11_1001"; --
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constant MIPS_FUNC_FMT_C_SEQ : t_mips_function := b"11_1010"; --
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constant MIPS_FUNC_FMT_C_NGL : t_mips_function := b"11_1011"; --
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constant MIPS_FUNC_FMT_C_LT : t_mips_function := b"11_1100"; --
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constant MIPS_FUNC_FMT_C_NGE : t_mips_function := b"11_1101"; --
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314 |
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constant MIPS_FUNC_FMT_C_LE : t_mips_function := b"11_1110"; --
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315 |
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constant MIPS_FUNC_FMT_C_NGT : t_mips_function := b"11_1111"; --
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316 |
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317 |
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-- _ _ ____ _ _ ____ ____ _ _
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318 |
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-- |\/| |___ |\/| | | |__/ \_/
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319 |
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-- | | |___ | | |__| | \ |
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320 |
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-- load from memory
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321 |
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constant MIPS_OPCODE_LB : t_mips_opcode := b"10_0000"; -- rt = *(char* )(rs + offset)
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322 |
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constant MIPS_OPCODE_LH : t_mips_opcode := b"10_0001"; -- rt = *(short* )(rs + offset)
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323 |
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constant MIPS_OPCODE_LWL : t_mips_opcode := b"10_0010"; -- rt = rt[15:0]|(*(short*)(rs + offset) << 16)
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324 |
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constant MIPS_OPCODE_LW : t_mips_opcode := b"10_0011"; -- rt = *(int* )(rs + offset)
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325 |
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constant MIPS_OPCODE_LBU : t_mips_opcode := b"10_0100"; -- rt = *(unsigned char* )(rs + offset)
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326 |
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constant MIPS_OPCODE_LHU : t_mips_opcode := b"10_0101"; -- rt = *(unsigned short* )(rs + offset)
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327 |
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constant MIPS_OPCODE_LWR : t_mips_opcode := b"10_0110"; -- rt = rt[31:16]|*(short*)(rs + offset)[15:0]
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328 |
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329 |
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-- store to memory
|
330 |
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constant MIPS_OPCODE_SB : t_mips_opcode := b"10_1000"; -- *(char* )(rs + offset) = rt
|
331 |
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constant MIPS_OPCODE_SH : t_mips_opcode := b"10_1001"; -- *(short* )(rs + offset) = rt
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332 |
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constant MIPS_OPCODE_SWL : t_mips_opcode := b"10_1010"; -- *(short* )(rs + offset)[31:16] = rt[31:16]
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333 |
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constant MIPS_OPCODE_SW : t_mips_opcode := b"10_1011"; -- *(int* )(rs + offset) = rt
|
334 |
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constant MIPS_OPCODE_SWR : t_mips_opcode := b"10_1110"; -- *(short* )(rs + offset)[15:0] = rt[15:0]
|
335 |
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|
336 |
|
|
-- coprocessor load from memory
|
337 |
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constant MIPS_OPCODE_LWC1 : t_mips_opcode := b"11_0001"; -- ft = *(int* )(base + offset)
|
338 |
|
|
constant MIPS_OPCODE_LWC2 : t_mips_opcode := b"11_0010";
|
339 |
|
|
|
340 |
|
|
-- coprocessor store to memory
|
341 |
|
|
constant MIPS_OPCODE_SWC1 : t_mips_opcode := b"11_1001"; -- *(int* )(base + offset) = ft
|
342 |
|
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|
343 |
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end package mips_instruction_set;
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