1 |
2 |
__alexs__ |
-- --------------------------------------------------------------------------
|
2 |
|
|
-- >>>>>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
3 |
|
|
-- --------------------------------------------------------------------------
|
4 |
|
|
-- TITLE: Plasma MAIN
|
5 |
|
|
-- AUTHOR: Alex Schoenberger (Alex.Schoenberger@ies.tu-darmstadt.de)
|
6 |
|
|
-- COMMENT: This project is based on Plasma CPU core by Steve Rhoads
|
7 |
|
|
--
|
8 |
|
|
-- www.ies.tu-darmstadt.de
|
9 |
|
|
-- TU Darmstadt
|
10 |
|
|
-- Institute for Integrated Systems
|
11 |
|
|
-- Merckstr. 25
|
12 |
|
|
--
|
13 |
|
|
-- 64283 Darmstadt - GERMANY
|
14 |
|
|
-- --------------------------------------------------------------------------
|
15 |
|
|
-- PROJECT: Plasma CPU core with FPU
|
16 |
|
|
-- FILENAME: plasma.vhd
|
17 |
|
|
-- --------------------------------------------------------------------------
|
18 |
|
|
-- COPYRIGHT:
|
19 |
|
|
-- This project is distributed by GPLv2.0
|
20 |
|
|
-- Software placed into the public domain by the author.
|
21 |
|
|
-- Software 'as is' without warranty. Author liable for nothing.
|
22 |
|
|
-- --------------------------------------------------------------------------
|
23 |
|
|
-- DESCRIPTION:
|
24 |
|
|
-- top of plasma design
|
25 |
|
|
--
|
26 |
|
|
-- SYNTHESIZABLE
|
27 |
|
|
--
|
28 |
|
|
----------------------------------------------------------------------------
|
29 |
|
|
-- Revision History
|
30 |
|
|
-- --------------------------------------------------------------------------
|
31 |
|
|
-- Revision Date Author CHANGES
|
32 |
|
|
-- 1.0 4/2014 AS initial
|
33 |
|
|
-- 2.0 5/2015 AS added branches: MIPS I or MIPS32r2
|
34 |
|
|
-- with and without FPU
|
35 |
|
|
-- --------------------------------------------------------------------------
|
36 |
|
|
library IEEE;
|
37 |
|
|
use IEEE.std_logic_1164.ALL;
|
38 |
|
|
|
39 |
|
|
entity plasma is
|
40 |
|
|
generic(
|
41 |
|
|
core_idx : natural := 0;
|
42 |
|
|
FPU_FLAG : string := "OF";
|
43 |
|
|
SIM_FLAG : string := "ON";
|
44 |
|
|
DEBUG_FLAG : string := "OF"
|
45 |
|
|
);
|
46 |
|
|
port(
|
47 |
|
|
clk : in std_logic;
|
48 |
|
|
rst : in std_logic;
|
49 |
|
|
instr_addr : out std_logic_vector(31 downto 0);
|
50 |
|
|
data_addr : out std_logic_vector(31 downto 0);
|
51 |
|
|
rd_mask : out std_logic_vector(3 downto 0);
|
52 |
|
|
wr_mask : out std_logic_vector(3 downto 0);
|
53 |
|
|
instr_stall : in std_logic;
|
54 |
|
|
data_stall : in std_logic;
|
55 |
|
|
instr_in : in std_logic_vector(31 downto 0);
|
56 |
|
|
data_to_cpu : in std_logic_vector(31 downto 0);
|
57 |
|
|
data_from_cpu : out std_logic_vector(31 downto 0)
|
58 |
|
|
);
|
59 |
|
|
end entity plasma;
|
60 |
|
|
|
61 |
|
|
|
62 |
|
|
library PLASMA;
|
63 |
|
|
use PLASMA.mips_instruction_set.t_mips_opcode;
|
64 |
|
|
use PLASMA.plasma_pack.ALL;
|
65 |
|
|
|
66 |
|
|
architecture structure_plasma of plasma is
|
67 |
|
|
|
68 |
|
|
|
69 |
|
|
signal reg_addr : t_reg_addr;
|
70 |
|
|
signal stall_src : t_stall_source;
|
71 |
|
|
|
72 |
|
|
signal unit_busy : t_unit_busy;
|
73 |
|
|
signal comp_out : std_logic;
|
74 |
|
|
|
75 |
|
|
-- ############ MEMORY CONTROL INTERN #####
|
76 |
|
|
signal mem_func : t_mips_opcode;
|
77 |
|
|
|
78 |
|
|
signal i_prog_addr : t_plasma_word;
|
79 |
|
|
signal i_data_addr : t_plasma_word;
|
80 |
|
|
signal instr : t_plasma_word;
|
81 |
|
|
|
82 |
|
|
signal prog_stall_in : std_logic;
|
83 |
|
|
signal data_stall_in : std_logic;
|
84 |
|
|
|
85 |
|
|
signal data_w : t_plasma_word;
|
86 |
|
|
signal data_r : t_plasma_word;
|
87 |
|
|
|
88 |
|
|
begin
|
89 |
|
|
|
90 |
|
|
|
91 |
|
|
SOFT_FPU: if FPU_FLAG = "OF" generate
|
92 |
|
|
|
93 |
|
|
signal unit_ctrl : t_plasma_subunits_ctrl;
|
94 |
|
|
signal mux_ctrl : t_plasma_mux_ctrl;
|
95 |
|
|
|
96 |
|
|
for u1_control: plasma_control_MIPSI use entity PLASMA.plasma_control_MIPSI(structure_plasma_control_MIPSI);
|
97 |
|
|
for u2_datapath: plasma_datapath_MIPSI use entity PLASMA.plasma_datapath_MIPSI(structure_plasma_datapath_MIPSI);
|
98 |
|
|
begin
|
99 |
|
|
|
100 |
|
|
u1_control: plasma_control_MIPSI
|
101 |
|
|
GENERIC MAP( core_idx => core_idx )
|
102 |
|
|
PORT MAP(
|
103 |
|
|
control.clk => clk, control.rst => rst,
|
104 |
|
|
instr_in => instr,
|
105 |
|
|
|
106 |
|
|
prog_stall => prog_stall_in, data_stall => data_stall_in,
|
107 |
|
|
|
108 |
|
|
comp_out => comp_out, unit_busy => unit_busy,
|
109 |
|
|
|
110 |
|
|
reg_addr => reg_addr, mux_ctrl => mux_ctrl,
|
111 |
|
|
stall_src => stall_src, unit_ctrl => unit_ctrl,
|
112 |
|
|
|
113 |
|
|
mem_func => mem_func
|
114 |
|
|
);
|
115 |
|
|
|
116 |
|
|
u2_datapath: plasma_datapath_MIPSI
|
117 |
|
|
GENERIC MAP( core_idx => core_idx,
|
118 |
|
|
SIM_FLAG => SIM_FLAG, DEBUG_FLAG => DEBUG_FLAG)
|
119 |
|
|
PORT MAP(
|
120 |
|
|
control.clk => clk, control.rst => rst,
|
121 |
|
|
|
122 |
|
|
reg_addr => reg_addr, mux_ctrl => mux_ctrl,
|
123 |
|
|
stall_src => stall_src,
|
124 |
|
|
|
125 |
|
|
comp_out => comp_out, unit_busy => unit_busy,
|
126 |
|
|
|
127 |
|
|
unit_ctrl => unit_ctrl,
|
128 |
|
|
|
129 |
|
|
instr_addr => i_prog_addr, data_addr => i_data_addr,
|
130 |
|
|
instr_in => instr,
|
131 |
|
|
data_from_mem => data_r, data_to_mem => data_w
|
132 |
|
|
);
|
133 |
|
|
|
134 |
|
|
end generate;
|
135 |
|
|
|
136 |
|
|
HARD_FPU: if FPU_FLAG = "ON" generate
|
137 |
|
|
|
138 |
|
|
signal unit_ctrl : t_plasma_subunits_ctrl;
|
139 |
|
|
signal fpu_ctrl : t_fpu_ctrl;
|
140 |
|
|
|
141 |
|
|
signal mux_ctrl : t_plasma_mux_ctrl;
|
142 |
|
|
signal mux_fpu : t_plasma_mux_fpu;
|
143 |
|
|
|
144 |
|
|
signal fpu_reg_addr : t_reg_addr;
|
145 |
|
|
signal fpu_cc : std_logic;
|
146 |
|
|
|
147 |
|
|
for u1_control: plasma_control_MIPSI_FPU use entity PLASMA.plasma_control_MIPSI_FPU(structure_plasma_control_MIPSI_FPU);
|
148 |
|
|
for u2_datapath: plasma_datapath_MIPSI_FPU use entity PLASMA.plasma_datapath_MIPSI_FPU(structure_plasma_datapath_MIPSI_FPU);
|
149 |
|
|
|
150 |
|
|
begin
|
151 |
|
|
|
152 |
|
|
u1_control: plasma_control_MIPSI_FPU
|
153 |
|
|
GENERIC MAP( core_idx => core_idx )
|
154 |
|
|
PORT MAP(
|
155 |
|
|
control.clk => clk, control.rst => rst,
|
156 |
|
|
instr_in => instr,
|
157 |
|
|
|
158 |
|
|
prog_stall => prog_stall_in, data_stall => data_stall_in,
|
159 |
|
|
|
160 |
|
|
comp_out => comp_out, fpu_cc => fpu_cc, unit_busy => unit_busy,
|
161 |
|
|
|
162 |
|
|
reg_addr => reg_addr, fpu_reg_addr => fpu_reg_addr,
|
163 |
|
|
|
164 |
|
|
mux_ctrl => mux_ctrl, mux_fpu => mux_fpu,
|
165 |
|
|
stall_src => stall_src, unit_ctrl => unit_ctrl, fpu_ctrl => fpu_ctrl,
|
166 |
|
|
|
167 |
|
|
mem_func => mem_func
|
168 |
|
|
);
|
169 |
|
|
|
170 |
|
|
u2_datapath: plasma_datapath_MIPSI_FPU
|
171 |
|
|
GENERIC MAP( core_idx => core_idx,
|
172 |
|
|
SIM_FLAG => SIM_FLAG, DEBUG_FLAG => DEBUG_FLAG)
|
173 |
|
|
PORT MAP(
|
174 |
|
|
control.clk => clk, control.rst => rst,
|
175 |
|
|
|
176 |
|
|
reg_addr => reg_addr, fpu_reg_addr => fpu_reg_addr,
|
177 |
|
|
mux_ctrl => mux_ctrl, mux_fpu => mux_fpu,
|
178 |
|
|
stall_src => stall_src,
|
179 |
|
|
|
180 |
|
|
comp_out => comp_out, fpu_cc => fpu_cc, unit_busy => unit_busy,
|
181 |
|
|
|
182 |
|
|
unit_ctrl => unit_ctrl, fpu_ctrl => fpu_ctrl,
|
183 |
|
|
|
184 |
|
|
instr_addr => i_prog_addr, data_addr => i_data_addr,
|
185 |
|
|
instr_in => instr,
|
186 |
|
|
data_from_mem => data_r, data_to_mem => data_w
|
187 |
|
|
);
|
188 |
|
|
|
189 |
|
|
end generate; -- FPU
|
190 |
|
|
|
191 |
|
|
-- _ _ ____ _ _ ____ ____ _ _ ____ ____ _ _ ___ ____ ____ _
|
192 |
|
|
-- |\/| |___ |\/| | | |__/ \_/ | | | |\ | | |__/ | | |
|
193 |
|
|
-- | | |___ | | |__| | \ | |___ |__| | \| | | \ |__| |___
|
194 |
|
|
u3_mem_ctrl: plasma_mem_ctrl
|
195 |
|
|
PORT MAP(
|
196 |
|
|
clk => clk, reset => rst,
|
197 |
|
|
|
198 |
|
|
mem_func => mem_func,
|
199 |
|
|
prog_addr_in => i_prog_addr, data_addr_in => i_data_addr,
|
200 |
|
|
data_w_in => data_w,
|
201 |
|
|
|
202 |
|
|
prog_stall_in => instr_stall, data_stall_in => data_stall,
|
203 |
|
|
prog_in => instr_in, data_r_in => data_to_cpu,
|
204 |
|
|
|
205 |
|
|
prog_stall_out => prog_stall_in, data_stall_out => data_stall_in,
|
206 |
|
|
prog_out => instr, data_r_out => data_r,
|
207 |
|
|
|
208 |
|
|
prog_addr_out => instr_addr, data_addr_out => data_addr,
|
209 |
|
|
wr_mask_out => wr_mask, rd_mask_out => rd_mask,
|
210 |
|
|
data_w_out => data_from_cpu
|
211 |
|
|
);
|
212 |
|
|
|
213 |
|
|
end architecture structure_plasma;
|