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__alexs__ |
-- --------------------------------------------------------------------------
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-- >>>>>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<<
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-- --------------------------------------------------------------------------
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-- TITLE: Plasma MEMORY CONTROL
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-- AUTHOR: Alex Schoenberger (Alex.Schoenberger@ies.tu-darmstadt.de)
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-- COMMENT: This project is based on Plasma CPU core by Steve Rhoads
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--
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-- www.ies.tu-darmstadt.de
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-- TU Darmstadt
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-- Institute for Integrated Systems
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-- Merckstr. 25
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--
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-- 64283 Darmstadt - GERMANY
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-- --------------------------------------------------------------------------
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-- PROJECT: Plasma CPU core with FPU
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-- FILENAME: plasma.vhd
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-- --------------------------------------------------------------------------
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-- COPYRIGHT:
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-- This project is distributed by GPLv2.0
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-- Software placed into the public domain by the author.
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-- Software 'as is' without warranty. Author liable for nothing.
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-- --------------------------------------------------------------------------
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-- DESCRIPTION:
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-- preparate data for memory access
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--
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-- SYNTHESIZABLE
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--
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----------------------------------------------------------------------------
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-- Revision History
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-- --------------------------------------------------------------------------
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-- Revision Date Author CHANGES
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-- 1.0 4/2014 AS initial
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-- 2.0 5/2015 AS works with MIPS commands directly
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-- --------------------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.ALL;
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library PLASMA;
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use PLASMA.mips_instruction_set.ALL;
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use PLASMA.plasma_pack.ALL;
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entity plasma_mem_ctrl is
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port(
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clk : in std_logic;
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reset : in std_logic;
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-- INPUT FROM PLASMA
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mem_func : in t_mips_opcode;
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prog_addr_in : in t_plasma_word;
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data_addr_in : in t_plasma_word;
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data_w_in : in t_plasma_word;
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-- INPUT FROM MEMORY
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prog_stall_in : in std_logic;
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data_stall_In : in std_logic;
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prog_in : in t_plasma_word;
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data_r_in : in t_plasma_word;
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-- OUTPUT TO PLASMA
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prog_stall_out : out std_logic;
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data_stall_out : out std_logic;
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prog_out : out t_plasma_word;
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data_r_out : out t_plasma_word;
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-- OUTPUT TO MEMORY
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prog_addr_out : out t_plasma_word;
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data_addr_out : out t_plasma_word;
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wr_mask_out : out t_plasma_mask;
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rd_mask_out : out t_plasma_mask;
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data_w_out : out t_plasma_word
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);
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end entity plasma_mem_ctrl;
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architecture structure_plasma_mem_ctrl of plasma_mem_ctrl is
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-- ___ ____ ___ ____ ___ ____ _ _ ____ _ _ ____ ____ _ _
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-- | \ |__| | |__| | | | |\/| |___ |\/| | | |__/ \_/
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-- |__/ | | | | | | |__| | | |___ | | |__| | \ |
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signal i_wr_mask : t_plasma_mask;
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signal i_rd_mask : t_plasma_mask;
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signal i_data_w : t_plasma_word;
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-- ___ ____ ___ ____ ___ ____ ___ _ ____ ____ _ _ ____
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-- | \ |__| | |__| | | | |__] | |__| [__ |\/| |__|
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-- |__/ | | | | | | |__| | |___ | | ___] | | | |
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signal i_data_r : t_plasma_word;
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begin
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-- ----------------------------------------------------------------------------------------------
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-- _____ _____ ____ _____ _____ __ __
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-- | __ \| __ \ / __ \ / ____| __ \ /\ | \/ |
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-- | |__) | |__) | | | | | __| |__) | / \ | \ / |
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-- | ___/| _ /| | | | | |_ | _ / / /\ \ | |\/| |
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-- | | | | \ \| |__| | |__| | | \ \ / ____ \| | | |
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-- |_| |_| \_\\____/ \_____|_| \_\/_/ \_\_| |_|
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-- ----------------------------------------------------------------------------------------------
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--
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-- FORWARDING ONLY, WORDS AS INPUT AND OUTPUT
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--
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-- ____ ___ ___ ____ ___ ____ ___ _ ____ ____ _ _ ____
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-- |__| | \ | \ |__/ | | | |__] | |__| [__ |\/| |__|
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-- | | |__/ |__/ | \ | |__| | |___ | | ___] | | | |
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prog_stall_out <= prog_stall_in; -- program memory stall
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prog_out <= prog_in; -- program data
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-- ____ ___ ___ ____ ___ ____ _ _ ____ _ _ ____ ____ _ _
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-- |__| | \ | \ |__/ | | | |\/| |___ |\/| | | |__/ \_/
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-- | | |__/ |__/ | \ | |__| | | |___ | | |__| | \ |
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prog_addr_out <= prog_addr_in; -- program address
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-- ----------------------------------------------------------------------------------------------
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-- _____ _______
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-- | __ \ /\|__ __|/\
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-- | | | | / \ | | / \
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-- | | | |/ /\ \ | | / /\ \
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-- | |__| / ____ \| |/ ____ \
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-- |_____/_/ \_\_/_/ \_\
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-- ----------------------------------------------------------------------------------------------
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--
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-- REGISTER STAGE AND MASK LOGIC
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--
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mem_read_write_process:
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process( mem_func, data_w_in, data_r_in )
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begin
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-- DEFAULT VALUES
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i_rd_mask <= (others => '0');
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i_wr_mask <= (others => '0');
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i_data_w <= PLASMA_ZERO_WORD;
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i_data_r <= PLASMA_ZERO_WORD;
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-- MEMORY ACCESS FUNCTION
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case mem_func is
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-- ____ ____ ____ ___
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-- |__/ |___ |__| | \
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-- | \ |___ | | |__/
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when MIPS_OPCODE_LW |
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MIPS_OPCODE_LWC1 |
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MIPS_OPCODE_LWL => i_rd_mask <= PLASMA_MASK_READ32;
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i_data_r <= data_r_in;
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-- when MIPS_OPCODE_LWL => i_rd_mask <= PLASMA_MASK_READ32L; -- COMPILER BUG !!
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-- i_data_w <= data_w_in;
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-- i_data_r <= data_r_in;
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-- when MIPS_OPCODE_LWR => i_rd_mask <= PLASMA_MASK_READ32R; -- COMPILER BUG !!
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-- i_data_w <= data_w_in;
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-- i_data_r <= data_r_in;
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when MIPS_OPCODE_LHU => i_rd_mask <= PLASMA_MASK_READ16;
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i_data_r(31 downto 16) <= (others => '0');
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i_data_r(15 downto 0) <= data_r_in(15 downto 0);
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when MIPS_OPCODE_LH => i_rd_mask <= PLASMA_MASK_READ16;
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i_data_r(31 downto 16) <= (others => data_r_in(15));
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i_data_r(15 downto 0) <= data_r_in(15 downto 0);
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when MIPS_OPCODE_LBU => i_rd_mask <= PLASMA_MASK_READ8;
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i_data_r(31 downto 8) <= (others => '0');
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i_data_r( 7 downto 0) <= data_r_in(7 downto 0);
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when MIPS_OPCODE_LB => i_rd_mask <= PLASMA_MASK_READ8;
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i_data_r(31 downto 8) <= (others => data_r_in(7));
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i_data_r( 7 downto 0) <= data_r_in(7 downto 0);
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-- _ _ _ ____ _ ___ ____
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-- | | | |__/ | | |___
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-- |_|_| | \ | | |___
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when MIPS_OPCODE_SW |
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MIPS_OPCODE_SWC1 |
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MIPS_OPCODE_SWL => i_wr_mask <= PLASMA_MASK_WRITE32;
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i_data_w <= data_w_in;
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-- when MIPS_OPCODE_SWL => i_wr_mask <= PLASMA_MASK_WRITE32L; -- COMPILER BUG !!
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-- i_data_w <= data_w_in;
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-- when MIPS_OPCODE_SWR => i_wr_mask <= PLASMA_MASK_WRITE32R; -- COMPILER BUG !!
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-- i_data_w <= data_w_in;
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when MIPS_OPCODE_SH => i_wr_mask <= PLASMA_MASK_WRITE16;
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--i_data_w(31 downto 16) <= (others => '0');
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i_data_w(31 downto 16) <= data_w_in(15 downto 0);
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i_data_w(15 downto 0) <= data_w_in(15 downto 0);
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when MIPS_OPCODE_SB => i_wr_mask <= PLASMA_MASK_WRITE8;
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-- i_data_w(31 downto 8) <= (others => '0');
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i_data_w(31 downto 24) <= data_w_in(7 downto 0);
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i_data_w(23 downto 16) <= data_w_in(7 downto 0);
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i_data_w(15 downto 8) <= data_w_in(7 downto 0);
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i_data_w( 7 downto 0) <= data_w_in(7 downto 0);
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when others => -- default values
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end case;
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end process;
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-- ADDRESS
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data_addr_out <= data_addr_in;
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-- STALL
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data_stall_out <= data_stall_in;
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-- READ
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rd_mask_out <= i_rd_mask;
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data_r_out <= i_data_r;
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-- WRITE
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wr_mask_out <= i_wr_mask;
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data_w_out <= i_data_w;
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end architecture structure_plasma_mem_ctrl;
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