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__alexs__ |
-- --------------------------------------------------------------------------
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-- >>>>>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<<
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-- --------------------------------------------------------------------------
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-- TITLE: Plasma ALU
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-- AUTHOR: Alex Schoenberger (Alex.Schoenberger@ies.tu-darmstadt.de)
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-- COMMENT: This project is based on Plasma CPU core by Steve Rhoads
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--
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-- www.ies.tu-darmstadt.de
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-- TU Darmstadt
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-- Institute for Integrated Systems
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-- Merckstr. 25
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--
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-- 64283 Darmstadt - GERMANY
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-- --------------------------------------------------------------------------
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-- PROJECT: Plasma CPU core with FPU
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-- FILENAME: plasma_alu.vhd
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-- --------------------------------------------------------------------------
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-- COPYRIGHT:
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-- This project is distributed by GPLv2.0
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-- Software placed into the public domain by the author.
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-- Software 'as is' without warranty. Author liable for nothing.
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-- --------------------------------------------------------------------------
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-- DESCRIPTION:
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-- implements ALU operation depending on instruction code:
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-- ADD, ADDU, SUB, SUBU, AND, OR, XOR, NOR, less than, less than signed
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--
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-- SYNTHESIZABLE
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--
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----------------------------------------------------------------------------
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-- Revision History
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-- --------------------------------------------------------------------------
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-- Revision Date Author CHANGES
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-- 1.0 4/2014 AS initial
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-- 2.0 5/2015 AS work with MIPS commands directly
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-- --------------------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.ALL;
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use IEEE.numeric_std.ALL;
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library PLASMA;
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use PLASMA.mips_instruction_set.ALL;
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use PLASMA.plasma_pack.ALL;
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entity plasma_alu is
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port(
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alu_a_in : in t_plasma_word;
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alu_b_in : in t_plasma_word;
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alu_func : in t_mips_function;
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alu_out : out t_plasma_word
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);
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end entity plasma_alu;
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--synthesis translate_off
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-- ____ _ _ _ _ _ _ ____ ___ _ ____ _ _
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-- [__ | |\/| | | | |__| | | | | |\ |
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-- ___] | | | |__| |___ | | | | |__| | \|
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architecture sim_alu of plasma_alu is
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signal eq, equ : Boolean;
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begin
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eq <= signed(alu_a_in) < signed(alu_b_in);
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equ <= unsigned(alu_a_in) < unsigned(alu_b_in);
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process( alu_a_in, alu_b_in, alu_func, eq, equ )
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begin
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alu_out <= PLASMA_ZERO_WORD; -- default value
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case alu_func(2 downto 0) is
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when "000" => alu_out <= std_logic_vector( signed(alu_a_in) + signed(alu_b_in)); -- ADD
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when "001" => alu_out <= std_logic_vector(unsigned(alu_a_in) + unsigned(alu_b_in)); -- ADDU
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when "010" => if alu_func(5 downto 3) = "100" then
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alu_out <= std_logic_vector( signed(alu_a_in) - signed(alu_b_in)); -- SUB
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else
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if eq then alu_out <= PLASMA_SET_WORD; end if; -- SLT
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end if;
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when "011" => if alu_func(5 downto 3) = "100" then
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alu_out <= std_logic_vector(unsigned(alu_a_in) - unsigned(alu_b_in)); -- SUBU
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else
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if equ then alu_out <= PLASMA_SET_WORD; end if; -- SLTU
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end if;
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when "100" => alu_out <= alu_a_in and alu_b_in; -- AND
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when "101" => alu_out <= alu_a_in or alu_b_in; -- OR
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when "110" => alu_out <= alu_a_in xor alu_b_in; -- XOR
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when "111" => if alu_func(5) ='1' then
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alu_out <= alu_a_in nor alu_b_in; -- NOR
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else
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alu_out <= std_logic_vector( signed(alu_a_in) + signed(alu_b_in)); -- LUI
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end if;
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when others =>
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end case;
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end process;
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end architecture sim_alu;
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--synthesis translate_on
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-- ____ ___ ____ ____
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-- |___ |__] | __ |__|
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-- | | |__] | |
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architecture FPGA_alu of plasma_alu is begin
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process( alu_a_in, alu_b_in, alu_func )
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variable temp_result : t_plasma_word;
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variable sign_xor : std_logic;
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begin
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alu_out <= PLASMA_ZERO_WORD; -- default value
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case alu_func(2 downto 0) is
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when "000" => alu_out <= std_logic_vector( signed(alu_a_in) + signed(alu_b_in)); -- ADD
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when "001" => alu_out <= std_logic_vector(unsigned(alu_a_in) + unsigned(alu_b_in)); -- ADDU
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when "010" => if alu_func(5 downto 3) = "100" then
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alu_out <= std_logic_vector( signed(alu_a_in) - signed(alu_b_in)); -- SUB
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else -- SLT
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temp_result := std_logic_vector(signed(alu_a_in) - signed(alu_b_in)); -- calculate difference
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sign_xor :=
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alu_a_in(PLASMA_DATA_WIDTH - 1) xor alu_b_in(PLASMA_DATA_WIDTH - 1); -- check for different sign bits
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if sign_xor = '0' then -- equal signs
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alu_out(0) <= temp_result(PLASMA_DATA_WIDTH - 1); -- pass sign of difference
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else -- different signs
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alu_out(0) <= alu_a_in(PLASMA_DATA_WIDTH - 1); -- if a < 0 -> a < b (because b > 0)
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end if; -- if a > 0 -> a > b (because b < 0)
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alu_out(PLASMA_DATA_WIDTH - 1 downto 1)
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<= PLASMA_ZERO_WORD(PLASMA_DATA_WIDTH - 1 downto 1); -- fill rest with zeros
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end if;
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when "011" => if alu_func(5 downto 3) = "100" then
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alu_out <= std_logic_vector(unsigned(alu_a_in) - unsigned(alu_b_in)); -- SUBU
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else -- SLTU
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temp_result := std_logic_vector(unsigned(alu_a_in) - unsigned(alu_b_in)); -- calculate difference
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sign_xor :=
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alu_a_in(PLASMA_DATA_WIDTH - 1) xor alu_b_in(PLASMA_DATA_WIDTH - 1); -- check for different sign bits
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if sign_xor = '0' then -- operands have equal signs
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alu_out(0) <= temp_result(PLASMA_DATA_WIDTH - 1); -- pass difference sign
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else -- operands have different signs
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alu_out(0) <= alu_b_in(PLASMA_DATA_WIDTH - 1); -- if MSB(a) = 1 then a > b (MSB(b) must be 0)
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end if; -- if MSB(a) = 0 then a < b (MSB(b) must be 1)
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alu_out(PLASMA_DATA_WIDTH - 1 downto 1)
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<= PLASMA_ZERO_WORD(PLASMA_DATA_WIDTH - 1 downto 1); -- fill rest with zeros
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end if;
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when "100" => alu_out <= alu_a_in and alu_b_in; -- AND
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when "101" => alu_out <= alu_a_in or alu_b_in; -- OR
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when "110" => alu_out <= alu_a_in xor alu_b_in; -- XOR
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when "111" => if alu_func(5) ='1' then
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alu_out <= alu_a_in nor alu_b_in; -- NOR
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else
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alu_out <= std_logic_vector( signed(alu_a_in) + signed(alu_b_in)); -- LUI
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end if;
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when others =>
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end case;
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end process;
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end architecture FPGA_alu;
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