1 |
2 |
__alexs__ |
-- --------------------------------------------------------------------------
|
2 |
|
|
-- >>>>>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
3 |
|
|
-- --------------------------------------------------------------------------
|
4 |
|
|
-- TITLE: Plasma register bank
|
5 |
|
|
-- AUTHOR: Alex Schoenberger (Alex.Schoenberger@ies.tu-darmstadt.de)
|
6 |
|
|
-- COMMENT: This project is based on Plasma CPU core by Steve Rhoads
|
7 |
|
|
--
|
8 |
|
|
-- www.ies.tu-darmstadt.de
|
9 |
|
|
-- TU Darmstadt
|
10 |
|
|
-- Institute for Integrated Systems
|
11 |
|
|
-- Merckstr. 25
|
12 |
|
|
--
|
13 |
|
|
-- 64283 Darmstadt - GERMANY
|
14 |
|
|
-- --------------------------------------------------------------------------
|
15 |
|
|
-- PROJECT: Plasma CPU core with FPU
|
16 |
|
|
-- FILENAME: plasma_reg_bank.vhd
|
17 |
|
|
-- --------------------------------------------------------------------------
|
18 |
|
|
-- COPYRIGHT:
|
19 |
|
|
-- This project is distributed by GPLv2.0
|
20 |
|
|
-- Software placed into the public domain by the author.
|
21 |
|
|
-- Software 'as is' without warranty. Author liable for nothing.
|
22 |
|
|
-- --------------------------------------------------------------------------
|
23 |
|
|
-- DESCRIPTION:
|
24 |
|
|
-- register set of plasma
|
25 |
|
|
--
|
26 |
|
|
-- SYNTHESIZABLE
|
27 |
|
|
--
|
28 |
|
|
----------------------------------------------------------------------------
|
29 |
|
|
-- Revision History
|
30 |
|
|
-- --------------------------------------------------------------------------
|
31 |
|
|
-- Revision Date Author CHANGES
|
32 |
|
|
-- 1.0 4/2014 AS initial
|
33 |
|
|
-- --------------------------------------------------------------------------
|
34 |
|
|
library IEEE;
|
35 |
|
|
use IEEE.std_logic_1164.ALL;
|
36 |
|
|
use IEEE.numeric_std.ALL;
|
37 |
|
|
|
38 |
|
|
library PLASMA;
|
39 |
|
|
use PLASMA.mips_instruction_set.ALL;
|
40 |
|
|
use PLASMA.plasma_pack.ALL;
|
41 |
|
|
|
42 |
|
|
|
43 |
|
|
entity plasma_reg_bank is
|
44 |
|
|
generic(
|
45 |
|
|
core_idx : natural := 0;
|
46 |
|
|
DEBUG_FLAG : string := "OF"
|
47 |
|
|
);
|
48 |
|
|
port(
|
49 |
|
|
control : in t_main_control;
|
50 |
|
|
reg_addr : in t_reg_addr;
|
51 |
|
|
reg_dest_new : in t_plasma_word;
|
52 |
|
|
reg_source_out : out t_plasma_word;
|
53 |
|
|
reg_target_out : out t_plasma_word
|
54 |
|
|
);
|
55 |
|
|
end entity plasma_reg_bank;
|
56 |
|
|
|
57 |
|
|
|
58 |
|
|
architecture structure_reg_bank of plasma_reg_bank is
|
59 |
|
|
|
60 |
|
|
-- register bank memory
|
61 |
|
|
signal mem_reg_bank : t_reg_bank;
|
62 |
|
|
|
63 |
|
|
-- write signal detection
|
64 |
|
|
signal dest_zero : std_logic;
|
65 |
|
|
signal write_en : std_logic;
|
66 |
|
|
|
67 |
|
|
begin
|
68 |
|
|
-- -------- WRITE ENABLE DETECTION -------------------------
|
69 |
|
|
dest_zero <= '1' when reg_addr.rd = MIPS_R_ZERO else '0'; -- rs0 is always zero
|
70 |
|
|
write_en <= (not dest_zero) and reg_addr.we; -- no write enable for rs0
|
71 |
|
|
|
72 |
|
|
-- write process is a synchronous process
|
73 |
|
|
write_process: process( control.clk )
|
74 |
|
|
begin
|
75 |
|
|
if rising_edge( control.clk ) then
|
76 |
|
|
if control.rst = '1' then
|
77 |
|
|
for i in 2**PLASMA_REG_ADDR_WIDTH - 1 downto 0 loop
|
78 |
|
|
mem_reg_bank( i ) <= PLASMA_ZERO_WORD;
|
79 |
|
|
end loop;
|
80 |
|
|
else
|
81 |
|
|
if write_en = '1' then
|
82 |
|
|
mem_reg_bank( to_integer(unsigned(reg_addr.rd)) ) <= reg_dest_new;
|
83 |
|
|
end if;
|
84 |
|
|
end if;
|
85 |
|
|
end if;
|
86 |
|
|
end process;
|
87 |
|
|
|
88 |
|
|
-- read access is asynchronous
|
89 |
|
|
reg_source_out <= mem_reg_bank( to_integer(unsigned(reg_addr.rs)) );
|
90 |
|
|
reg_target_out <= mem_reg_bank( to_integer(unsigned(reg_addr.rt)) );
|
91 |
|
|
|
92 |
|
|
-- ############ DEBUGGING #############
|
93 |
|
|
--pragma translate_off
|
94 |
|
|
--synthesis translate_off
|
95 |
|
|
rb_debug: if DEBUG_FLAG = "ON" generate
|
96 |
|
|
|
97 |
|
|
signal i_addr : t_mips_reg_addr;
|
98 |
|
|
signal i_data : t_plasma_word;
|
99 |
|
|
|
100 |
|
|
begin
|
101 |
|
|
debug_process: process( control.clk )
|
102 |
|
|
begin
|
103 |
|
|
if rising_edge( control.clk ) then
|
104 |
|
|
if control.rst = '1' then
|
105 |
|
|
i_addr <= (others => '0');
|
106 |
|
|
i_data <= (others => '0');
|
107 |
|
|
else
|
108 |
|
|
if write_en = '1' then
|
109 |
|
|
i_addr <= reg_addr.rd;
|
110 |
|
|
i_data <= reg_dest_new;
|
111 |
|
|
|
112 |
|
|
if (i_addr /= reg_addr.rd) or (i_data /= reg_dest_new) then
|
113 |
|
|
report integer'image( core_idx ) &
|
114 |
|
|
" Addr " & sv2string(debug_prog_addr) &
|
115 |
|
|
" RB " & sv2reg(reg_addr.rd) & " " & sv2string(reg_dest_new);
|
116 |
|
|
end if;
|
117 |
|
|
end if;
|
118 |
|
|
end if;
|
119 |
|
|
end if;
|
120 |
|
|
end process;
|
121 |
|
|
end generate;
|
122 |
|
|
|
123 |
|
|
plasma_rbank(core_idx).we <= reg_addr.we;
|
124 |
|
|
plasma_rbank(core_idx).zero <= mem_reg_bank(0);
|
125 |
|
|
plasma_rbank(core_idx).at <= mem_reg_bank(1);
|
126 |
|
|
plasma_rbank(core_idx).v(0) <= mem_reg_bank(2);
|
127 |
|
|
plasma_rbank(core_idx).v(1) <= mem_reg_bank(3);
|
128 |
|
|
plasma_rbank(core_idx).a(0) <= mem_reg_bank(4);
|
129 |
|
|
plasma_rbank(core_idx).a(1) <= mem_reg_bank(5);
|
130 |
|
|
plasma_rbank(core_idx).a(2) <= mem_reg_bank(6);
|
131 |
|
|
plasma_rbank(core_idx).a(3) <= mem_reg_bank(7);
|
132 |
|
|
plasma_rbank(core_idx).t(0) <= mem_reg_bank(8);
|
133 |
|
|
plasma_rbank(core_idx).t(1) <= mem_reg_bank(9);
|
134 |
|
|
plasma_rbank(core_idx).t(2) <= mem_reg_bank(10);
|
135 |
|
|
plasma_rbank(core_idx).t(3) <= mem_reg_bank(11);
|
136 |
|
|
plasma_rbank(core_idx).t(4) <= mem_reg_bank(12);
|
137 |
|
|
plasma_rbank(core_idx).t(5) <= mem_reg_bank(13);
|
138 |
|
|
plasma_rbank(core_idx).t(6) <= mem_reg_bank(14);
|
139 |
|
|
plasma_rbank(core_idx).t(7) <= mem_reg_bank(15);
|
140 |
|
|
plasma_rbank(core_idx).s(0) <= mem_reg_bank(16);
|
141 |
|
|
plasma_rbank(core_idx).s(1) <= mem_reg_bank(17);
|
142 |
|
|
plasma_rbank(core_idx).s(2) <= mem_reg_bank(18);
|
143 |
|
|
plasma_rbank(core_idx).s(3) <= mem_reg_bank(19);
|
144 |
|
|
plasma_rbank(core_idx).s(4) <= mem_reg_bank(20);
|
145 |
|
|
plasma_rbank(core_idx).s(5) <= mem_reg_bank(21);
|
146 |
|
|
plasma_rbank(core_idx).s(6) <= mem_reg_bank(22);
|
147 |
|
|
plasma_rbank(core_idx).s(7) <= mem_reg_bank(23);
|
148 |
|
|
plasma_rbank(core_idx).t(8) <= mem_reg_bank(24);
|
149 |
|
|
plasma_rbank(core_idx).t(9) <= mem_reg_bank(25);
|
150 |
|
|
plasma_rbank(core_idx).k(0) <= mem_reg_bank(26);
|
151 |
|
|
plasma_rbank(core_idx).k(1) <= mem_reg_bank(27);
|
152 |
|
|
plasma_rbank(core_idx).gp <= mem_reg_bank(28);
|
153 |
|
|
plasma_rbank(core_idx).sp <= mem_reg_bank(29);
|
154 |
|
|
plasma_rbank(core_idx).s(8) <= mem_reg_bank(30);
|
155 |
|
|
plasma_rbank(core_idx).ra <= mem_reg_bank(31);
|
156 |
|
|
--synthesis translate_on
|
157 |
|
|
--pragma translate_on
|
158 |
|
|
|
159 |
|
|
end architecture structure_reg_bank;
|