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feddischso |
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---- ----
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---- PLB2WB-Bridge ----
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---- ----
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---- This file is part of the PLB-to-WB-Bridge project ----
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---- http://opencores.org/project,plb2wbbridge ----
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---- ----
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---- Description ----
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---- Implementation of a PLB-to-WB-Bridge according to ----
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---- PLB-to-WB Bridge specification document. ----
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---- ----
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---- To Do: ----
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---- Nothing ----
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---- ----
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---- Author(s): ----
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---- - Christian Haettich ----
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---- feddischson@opencores.org ----
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---- ----
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----------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2010 Authors ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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----------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_unsigned.all;
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library plb2wb_bridge_v1_00_a;
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use plb2wb_bridge_v1_00_a.all;
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entity top is
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generic
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(
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SYNCHRONY : boolean := false; -- true = synchron, false = asynchron!
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-- PLB Parameters -----------------------------------
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C_BASEADDR : std_logic_vector := X"FFFFFFFF";
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C_HIGHADDR : std_logic_vector := X"00000000";
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C_STATUS_BASEADDR : std_logic_vector := X"FFFFFFFF";
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C_STATUS_HIGHADDR : std_logic_vector := X"00000000";
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C_SPLB_AWIDTH : integer := 32;
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C_SPLB_DWIDTH : integer := 128;
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C_SPLB_NUM_MASTERS : integer := 8;
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C_SPLB_MID_WIDTH : integer := 3;
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C_SPLB_NATIVE_DWIDTH : integer := 32;
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C_SPLB_SUPPORT_BUR_LINE : integer := 1;
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C_SPLB_SUPPORT_ADR_PIPE : integer := 1;
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-- WB Parameters -----------------------------------
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WB_DAT_W : integer := 32;
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WB_ADR_W : integer := 32;
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WB_TIMEOUT_CYCLES : integer := 32;
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WB_ADR_OFFSET : std_logic_vector := X"f0000000";
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WB_ADR_OFFSET_NEG : std_logic := '0';
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WB_PIC_INTS : integer := 32;
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WB_PIC_INT_LEVEL : std_logic := '1';
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WB_SUPPORT_BLOCK : integer := 1
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);
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port(
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PLB2WB_IRQ : out std_logic;
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-- WB Signals ---------------------------------------
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wb_clk_i : in std_logic;
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wb_rst_i : in std_logic;
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wb_dat_i : in std_logic_vector( WB_DAT_W-1 downto 0 );
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wb_dat_o : out std_logic_vector( WB_DAT_W-1 downto 0 );
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wb_adr_o : out std_logic_vector( WB_ADR_W-1 downto 0 );
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wb_sel_o : out std_logic_vector( WB_DAT_W/8-1 downto 0 );
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wb_we_o : out std_logic;
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wb_cyc_o : out std_logic;
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wb_stb_o : out std_logic;
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wb_ack_i : in std_logic;
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wb_err_i : in std_logic;
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wb_rty_i : in std_logic;
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wb_lock_o : out std_logic;
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wb_pic_int_i : in std_logic_vector( WB_PIC_INTS-1 downto 0 );
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-- PLB Signals --------------------------------------
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SPLB_Clk : in std_logic;
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SPLB_Rst : in std_logic;
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PLB_ABus : in std_logic_vector( 0 to 31 );
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PLB_UABus : in std_logic_vector( 0 to 31 );
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PLB_PAValid : in std_logic;
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PLB_SAValid : in std_logic;
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PLB_rdPrim : in std_logic;
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PLB_wrPrim : in std_logic;
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PLB_masterID : in std_logic_vector( 0 to C_SPLB_MID_WIDTH-1 );
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PLB_abort : in std_logic;
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PLB_busLock : in std_logic;
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PLB_RNW : in std_logic;
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PLB_BE : in std_logic_vector( 0 to C_SPLB_DWIDTH/8-1 );
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PLB_MSize : in std_logic_vector( 0 to 1 );
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PLB_size : in std_logic_vector( 0 to 3 );
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PLB_type : in std_logic_vector( 0 to 2 );
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PLB_lockErr : in std_logic;
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PLB_wrDBus : in std_logic_vector( 0 to C_SPLB_DWIDTH-1 );
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PLB_wrBurst : in std_logic;
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PLB_rdBurst : in std_logic;
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PLB_wrPendReq : in std_logic;
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PLB_rdPendReq : in std_logic;
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PLB_wrPendPri : in std_logic_vector( 0 to 1 );
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PLB_rdPendPri : in std_logic_vector( 0 to 1 );
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PLB_reqPri : in std_logic_vector( 0 to 1 );
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PLB_TAttribute : in std_logic_vector( 0 to 15 );
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Sl_addrAck : out std_logic;
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Sl_SSize : out std_logic_vector( 0 to 1 );
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Sl_wait : out std_logic;
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Sl_rearbitrate : out std_logic;
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Sl_wrDAck : out std_logic;
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Sl_wrComp : out std_logic;
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Sl_wrBTerm : out std_logic;
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Sl_rdDBus : out std_logic_vector( 0 to C_SPLB_DWIDTH-1 );
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Sl_rdWdAddr : out std_logic_vector( 0 to 3 );
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Sl_rdDAck : out std_logic;
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Sl_rdComp : out std_logic;
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Sl_rdBTerm : out std_logic;
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Sl_MBusy : out std_logic_vector( 0 to C_SPLB_NUM_MASTERS-1 );
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Sl_MWrErr : out std_logic_vector( 0 to C_SPLB_NUM_MASTERS-1 );
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Sl_MRdErr : out std_logic_vector( 0 to C_SPLB_NUM_MASTERS-1 );
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Sl_MIRQ : out std_logic_vector( 0 to C_SPLB_NUM_MASTERS-1 )
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);
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end entity top;
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architecture imp of top is
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begin
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bridge : entity plb2wb_bridge_v1_00_a.plb2wb_bridge(IMP)
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generic map
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(
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SYNCHRONY => SYNCHRONY ,
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C_BASEADDR => C_BASEADDR ,
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C_HIGHADDR => C_HIGHADDR ,
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C_STATUS_BASEADDR => C_STATUS_BASEADDR ,
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C_STATUS_HIGHADDR => C_STATUS_HIGHADDR ,
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C_SPLB_AWIDTH => C_SPLB_AWIDTH ,
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C_SPLB_DWIDTH => C_SPLB_DWIDTH ,
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C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS ,
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C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH ,
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C_SPLB_NATIVE_DWIDTH => C_SPLB_NATIVE_DWIDTH ,
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C_SPLB_SUPPORT_BUR_LINE => C_SPLB_SUPPORT_BUR_LINE ,
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C_SPLB_SUPPORT_ADR_PIPE => C_SPLB_SUPPORT_ADR_PIPE,
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WB_DAT_W => WB_DAT_W ,
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WB_ADR_W => WB_ADR_W ,
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WB_TIMEOUT_CYCLES => WB_TIMEOUT_CYCLES ,
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WB_ADR_OFFSET => WB_ADR_OFFSET ,
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WB_ADR_OFFSET_NEG => WB_ADR_OFFSET_NEG ,
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WB_PIC_INTS => WB_PIC_INTS ,
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WB_PIC_INT_LEVEL => WB_PIC_INT_LEVEL ,
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WB_SUPPORT_BLOCK => WB_SUPPORT_BLOCK
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)
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port map
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(
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PLB2WB_IRQ => PLB2WB_IRQ ,
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wb_clk_i => wb_clk_i ,
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wb_rst_i => wb_rst_i ,
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wb_dat_i => wb_dat_i ,
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wb_dat_o => wb_dat_o ,
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wb_adr_o => wb_adr_o ,
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wb_sel_o => wb_sel_o ,
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wb_we_o => wb_we_o ,
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wb_cyc_o => wb_cyc_o ,
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wb_stb_o => wb_stb_o ,
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wb_ack_i => wb_ack_i ,
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wb_err_i => wb_err_i ,
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wb_rty_i => wb_rty_i ,
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wb_lock_o => wb_lock_o ,
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wb_pic_int_i => wb_pic_int_i ,
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SPLB_Clk => SPLB_Clk ,
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SPLB_Rst => SPLB_Rst ,
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PLB_ABus => PLB_ABus ,
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PLB_UABus => PLB_UABus ,
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PLB_PAValid => PLB_PAValid ,
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PLB_SAValid => PLB_SAValid ,
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PLB_rdPrim => PLB_rdPrim ,
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PLB_wrPrim => PLB_wrPrim ,
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PLB_masterID => PLB_masterID ,
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PLB_abort => PLB_abort ,
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PLB_busLock => PLB_busLock ,
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PLB_RNW => PLB_RNW ,
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PLB_BE => PLB_BE ,
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PLB_MSize => PLB_MSize ,
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PLB_size => PLB_size ,
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PLB_type => PLB_type ,
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PLB_lockErr => PLB_lockErr ,
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PLB_wrDBus => PLB_wrDBus ,
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PLB_wrBurst => PLB_wrBurst ,
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PLB_rdBurst => PLB_rdBurst ,
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PLB_wrPendReq => PLB_wrPendReq ,
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PLB_rdPendReq => PLB_rdPendReq ,
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PLB_wrPendPri => PLB_wrPendPri ,
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PLB_rdPendPri => PLB_rdPendPri ,
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PLB_reqPri => PLB_reqPri ,
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PLB_TAttribute => PLB_TAttribute ,
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Sl_addrAck => Sl_addrAck ,
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Sl_SSize => Sl_SSize ,
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Sl_wait => Sl_wait ,
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Sl_rearbitrate => Sl_rearbitrate ,
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Sl_wrDAck => Sl_wrDAck ,
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Sl_wrComp => Sl_wrComp ,
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Sl_wrBTerm => Sl_wrBTerm ,
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Sl_rdDBus => Sl_rdDBus ,
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Sl_rdWdAddr => Sl_rdWdAddr ,
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Sl_rdDAck => Sl_rdDAck ,
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Sl_rdComp => Sl_rdComp ,
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Sl_rdBTerm => Sl_rdBTerm ,
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Sl_MBusy => Sl_MBusy ,
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Sl_MWrErr => Sl_MWrErr ,
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Sl_MRdErr => Sl_MRdErr ,
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Sl_MIRQ => Sl_MIRQ
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);
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end architecture imp;
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