| 1 |
2 |
feddischso |
----------------------------------------------------------------------
|
| 2 |
|
|
---- ----
|
| 3 |
|
|
---- PLB2WB-Bridge ----
|
| 4 |
|
|
---- ----
|
| 5 |
|
|
---- This file is part of the PLB-to-WB-Bridge project ----
|
| 6 |
|
|
---- http://opencores.org/project,plb2wbbridge ----
|
| 7 |
|
|
---- ----
|
| 8 |
|
|
---- Description ----
|
| 9 |
|
|
---- Implementation of a PLB-to-WB-Bridge according to ----
|
| 10 |
|
|
---- PLB-to-WB Bridge specification document. ----
|
| 11 |
|
|
---- ----
|
| 12 |
|
|
---- To Do: ----
|
| 13 |
|
|
---- Nothing ----
|
| 14 |
|
|
---- ----
|
| 15 |
|
|
---- Author(s): ----
|
| 16 |
|
|
---- - Christian Haettich ----
|
| 17 |
|
|
---- feddischson@opencores.org ----
|
| 18 |
|
|
---- ----
|
| 19 |
|
|
----------------------------------------------------------------------
|
| 20 |
|
|
---- ----
|
| 21 |
|
|
---- Copyright (C) 2010 Authors ----
|
| 22 |
|
|
---- ----
|
| 23 |
|
|
---- This source file may be used and distributed without ----
|
| 24 |
|
|
---- restriction provided that this copyright statement is not ----
|
| 25 |
|
|
---- removed from the file and that any derivative work contains ----
|
| 26 |
|
|
---- the original copyright notice and the associated disclaimer. ----
|
| 27 |
|
|
---- ----
|
| 28 |
|
|
---- This source file is free software; you can redistribute it ----
|
| 29 |
|
|
---- and/or modify it under the terms of the GNU Lesser General ----
|
| 30 |
|
|
---- Public License as published by the Free Software Foundation; ----
|
| 31 |
|
|
---- either version 2.1 of the License, or (at your option) any ----
|
| 32 |
|
|
---- later version. ----
|
| 33 |
|
|
---- ----
|
| 34 |
|
|
---- This source is distributed in the hope that it will be ----
|
| 35 |
|
|
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
|
| 36 |
|
|
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
|
| 37 |
|
|
---- PURPOSE. See the GNU Lesser General Public License for more ----
|
| 38 |
|
|
---- details. ----
|
| 39 |
|
|
---- ----
|
| 40 |
|
|
---- You should have received a copy of the GNU Lesser General ----
|
| 41 |
|
|
---- Public License along with this source; if not, download it ----
|
| 42 |
|
|
---- from http://www.opencores.org/lgpl.shtml ----
|
| 43 |
|
|
---- ----
|
| 44 |
|
|
----------------------------------------------------------------------
|
| 45 |
|
|
|
| 46 |
|
|
|
| 47 |
|
|
library ieee;
|
| 48 |
|
|
use ieee.std_logic_1164.all;
|
| 49 |
|
|
use ieee.std_logic_arith.all;
|
| 50 |
|
|
use ieee.std_logic_unsigned.all;
|
| 51 |
|
|
|
| 52 |
|
|
|
| 53 |
|
|
library plb2wb_bridge_v1_00_a;
|
| 54 |
|
|
use plb2wb_bridge_v1_00_a.plb2wb_pkg.all;
|
| 55 |
|
|
|
| 56 |
|
|
|
| 57 |
|
|
|
| 58 |
|
|
|
| 59 |
|
|
|
| 60 |
|
|
entity fifo_rdat is
|
| 61 |
|
|
generic
|
| 62 |
|
|
(
|
| 63 |
|
|
SYNCHRONY : boolean := true; -- true = synchron
|
| 64 |
|
|
-- false = asynchron
|
| 65 |
|
|
WB_DWIDTH : integer range WB_DWIDTH_MIN to WB_DWIDTH_MAX := 32
|
| 66 |
|
|
);
|
| 67 |
|
|
port(
|
| 68 |
|
|
rd_en : in std_logic := 'X';
|
| 69 |
|
|
wr_en : in std_logic := 'X';
|
| 70 |
|
|
wr_clk : in std_logic := 'X';
|
| 71 |
|
|
rst : in std_logic := 'X';
|
| 72 |
|
|
rd_clk : in std_logic := 'X';
|
| 73 |
|
|
din : in std_logic_vector ( WB_DWIDTH+1-1 downto 0 );
|
| 74 |
|
|
dout : out std_logic_vector ( WB_DWIDTH+1-1 downto 0 );
|
| 75 |
|
|
full : out std_logic;
|
| 76 |
|
|
empty : out std_logic;
|
| 77 |
|
|
almost_empty : out std_logic
|
| 78 |
|
|
);
|
| 79 |
|
|
end entity fifo_rdat;
|
| 80 |
|
|
|
| 81 |
|
|
|
| 82 |
|
|
|
| 83 |
|
|
|
| 84 |
|
|
architecture IMP of fifo_rdat is
|
| 85 |
|
|
|
| 86 |
|
|
|
| 87 |
|
|
|
| 88 |
|
|
component fifo_rdat_cc_32 is
|
| 89 |
|
|
port (
|
| 90 |
|
|
rd_en : in STD_LOGIC := 'X';
|
| 91 |
|
|
wr_en : in STD_LOGIC := 'X';
|
| 92 |
|
|
full : out STD_LOGIC;
|
| 93 |
|
|
empty : out STD_LOGIC;
|
| 94 |
|
|
almost_empty : out STD_LOGIC;
|
| 95 |
|
|
clk : in STD_LOGIC := 'X';
|
| 96 |
|
|
rst : in STD_LOGIC := 'X';
|
| 97 |
|
|
dout : out STD_LOGIC_VECTOR ( RBUF_DWIDTH32-1 downto 0 );
|
| 98 |
|
|
din : in STD_LOGIC_VECTOR ( RBUF_DWIDTH32-1 downto 0 )
|
| 99 |
|
|
);
|
| 100 |
|
|
end component fifo_rdat_cc_32;
|
| 101 |
|
|
|
| 102 |
|
|
|
| 103 |
|
|
component fifo_rdat_ic_32 is
|
| 104 |
|
|
port (
|
| 105 |
|
|
rd_en : in STD_LOGIC := 'X';
|
| 106 |
|
|
wr_en : in STD_LOGIC := 'X';
|
| 107 |
|
|
full : out STD_LOGIC;
|
| 108 |
|
|
empty : out STD_LOGIC;
|
| 109 |
|
|
almost_empty : out STD_LOGIC;
|
| 110 |
|
|
wr_clk : in STD_LOGIC := 'X';
|
| 111 |
|
|
rst : in STD_LOGIC := 'X';
|
| 112 |
|
|
rd_clk : in STD_LOGIC := 'X';
|
| 113 |
|
|
dout : out STD_LOGIC_VECTOR ( RBUF_DWIDTH32-1 downto 0 );
|
| 114 |
|
|
din : in STD_LOGIC_VECTOR ( RBUF_DWIDTH32-1 downto 0 )
|
| 115 |
|
|
);
|
| 116 |
|
|
end component fifo_rdat_ic_32;
|
| 117 |
|
|
|
| 118 |
|
|
|
| 119 |
|
|
begin
|
| 120 |
|
|
|
| 121 |
|
|
|
| 122 |
|
|
|
| 123 |
|
|
|
| 124 |
|
|
fifo1: if ( SYNCHRONY = true and WB_DWIDTH = RBUF_DWIDTH32-1 ) generate
|
| 125 |
|
|
U_fifo_cc : fifo_rdat_cc_32
|
| 126 |
|
|
port map(
|
| 127 |
|
|
rd_en => rd_en,
|
| 128 |
|
|
wr_en => wr_en,
|
| 129 |
|
|
full => full,
|
| 130 |
|
|
empty => empty,
|
| 131 |
|
|
almost_empty => almost_empty,
|
| 132 |
|
|
clk => rd_clk, -- rd_clk must be the same than wr_clk
|
| 133 |
|
|
rst => rst,
|
| 134 |
|
|
dout => dout,
|
| 135 |
|
|
din => din
|
| 136 |
|
|
);
|
| 137 |
|
|
end generate fifo1;
|
| 138 |
|
|
|
| 139 |
|
|
fifo2: if ( SYNCHRONY = false and WB_DWIDTH = RBUF_DWIDTH32-1 ) generate
|
| 140 |
|
|
U_fifo_ic : fifo_rdat_ic_32
|
| 141 |
|
|
port map(
|
| 142 |
|
|
rd_en => rd_en,
|
| 143 |
|
|
wr_en => wr_en,
|
| 144 |
|
|
full => full,
|
| 145 |
|
|
empty => empty,
|
| 146 |
|
|
almost_empty => almost_empty,
|
| 147 |
|
|
rd_clk => rd_clk,
|
| 148 |
|
|
wr_clk => wr_clk,
|
| 149 |
|
|
rst => rst,
|
| 150 |
|
|
dout => dout,
|
| 151 |
|
|
din => din
|
| 152 |
|
|
);
|
| 153 |
|
|
end generate fifo2;
|
| 154 |
|
|
|
| 155 |
|
|
|
| 156 |
|
|
|
| 157 |
|
|
|
| 158 |
|
|
end architecture IMP;
|
| 159 |
|
|
|
