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[/] [plb2wbbridge/] [trunk/] [systems/] [EDK_Libs/] [WishboneIPLib/] [pcores/] [plb2wb_bridge_v1_00_a/] [hdl/] [vhdl/] [plb2wb_fifo.vhd] - Blame information for rev 2

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1 2 feddischso 
----------------------------------------------------------------------
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----                                                              ----
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----  PLB2WB-Bridge                                               ----
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----                                                              ----
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----  This file is part of the PLB-to-WB-Bridge project           ----
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----  http://opencores.org/project,plb2wbbridge                   ----
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----                                                              ----
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----  Description                                                 ----
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----  Implementation of a PLB-to-WB-Bridge according to           ----
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----  PLB-to-WB Bridge specification document.                    ----
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----                                                              ----
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----  To Do:                                                      ----
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----   Nothing                                                    ----
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----                                                              ----
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----  Author(s):                                                  ----
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----      - Christian Haettich                                    ----
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----        feddischson@opencores.org                             ----
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----                                                              ----
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----------------------------------------------------------------------
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----                                                              ----
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---- Copyright (C) 2010 Authors                                   ----
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----                                                              ----
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---- This source file may be used and distributed without         ----
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---- restriction provided that this copyright statement is not    ----
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---- removed from the file and that any derivative work contains  ----
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---- the original copyright notice and the associated disclaimer. ----
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----                                                              ----
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---- This source file is free software; you can redistribute it   ----
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---- and/or modify it under the terms of the GNU Lesser General   ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any   ----
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---- later version.                                               ----
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----                                                              ----
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---- This source is distributed in the hope that it will be       ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
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---- PURPOSE.  See the GNU Lesser General Public License for more ----
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---- details.                                                     ----
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----                                                              ----
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---- You should have received a copy of the GNU Lesser General    ----
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---- Public License along with this source; if not, download it   ----
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---- from http://www.opencores.org/lgpl.shtml                     ----
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----                                                              ----
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----------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.ALL;
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entity plb2wb_fifo is
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   generic(
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      DATA_W : natural := 32;
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      ADDR_W : natural := 4
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   );
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   port(
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      clk            : IN     std_logic;
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      rst            : IN     std_logic;
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      rd_en          : IN     std_logic;
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      wr_en          : IN     std_logic;
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      din            : IN     std_logic_vector( DATA_W-1 downto 0 );
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      dout           : OUT    std_logic_vector( DATA_W-1 downto 0 );
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      empty          : OUT    std_logic;
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      full           : OUT    std_logic
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   );
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end entity plb2wb_fifo;
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architecture IMP of plb2wb_fifo is
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   type fifo_array_type is array( 2**ADDR_W-1 downto 0 )
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      of std_logic_vector( DATA_W-1 downto 0 );
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   type state_type is record
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      read_pointer   : std_logic_vector( ADDR_W-1 downto 0 );
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      write_pointer  : std_logic_vector( ADDR_W-1 downto 0 );
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      full           : std_logic;
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      empty          : std_logic;
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   end record;
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   signal current_state, next_state : state_type         := -- to avoid modelsim warning at time: 0ps, iteration 0
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   ( read_pointer => ( others => '0' ), write_pointer => ( others => '0' ), full => '0', empty => '0' );
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   signal fifo_array                : fifo_array_type;
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   signal read_write_select         : std_logic_vector( 1 downto 0 );
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   signal rp_plus_1                 : std_logic_vector( ADDR_W-1 downto 0 );
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   signal wp_plus_1                 : std_logic_vector( ADDR_W-1 downto 0 );
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begin
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   n_state : process( clk, rst ) begin
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      if rst = '1' then
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         current_state.read_pointer    <= ( others => '0' );
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         current_state.write_pointer   <= ( others => '0' );
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         current_state.full            <= '0';
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         current_state.empty           <= '1';
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      elsif clk'event and clk='1' then
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         current_state <= next_state;
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      end if;
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   end process;
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   wp_plus_1         <= std_logic_vector( unsigned (current_state.write_pointer) +1 );
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   rp_plus_1         <= std_logic_vector( unsigned (current_state.read_pointer)  +1 );
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   read_write_select <= wr_en & rd_en  ;
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   states : process( current_state, read_write_select, wp_plus_1, rp_plus_1 ) begin
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      next_state <= current_state;
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      case read_write_select is
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         when "00" =>   -- nothing to do
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         when "01" =>   -- read
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            if current_state.empty /= '1' then
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               next_state.read_pointer  <= rp_plus_1;
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               next_state.full          <= '0';
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               if rp_plus_1 = current_state.write_pointer then
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                  next_state.empty <= '1';
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               end if;
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            end if;
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         when "10" =>   -- write
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            if current_state.full /= '1' then
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               next_state.write_pointer <= wp_plus_1;
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               next_state.empty         <= '0';
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               if wp_plus_1 = current_state.read_pointer then
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                  next_state.full <= '1';
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               end if;
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            end if;
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         when others =>  -- read and write
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            next_state.write_pointer <= wp_plus_1;
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            next_state.read_pointer  <= rp_plus_1;
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         end case;
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   end process;
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   write_fifo : process( clk, rst ) begin
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      if rst = '1' then
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         fifo_array  <= ( others => ( others => '0' ) );
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      elsif clk'event and clk='1' then
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         if wr_en = '1' and current_state.full = '0' then
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            fifo_array( to_integer( unsigned( current_state.write_pointer ))) <= din;
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         end if;
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      end if;
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   end process;
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   dout     <= fifo_array( to_integer( unsigned( current_state.read_pointer ) ) );
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   full     <= current_state.full;
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   empty    <= current_state.empty;
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end architecture IMP;
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