1 |
2 |
feddischso |
|
2 |
|
|
CUR_DIR=$(shell pwd)
|
3 |
|
|
SIM_DIR=$(CUR_DIR)/..
|
4 |
|
|
XPS_PROJ_DIR=$(CUR_DIR)/../..
|
5 |
|
|
LIB_DIR=$(CUR_DIR)/../../../EDK_Libs
|
6 |
|
|
|
7 |
|
|
PLB2WB_LIB_DIR=$(LIB_DIR)/WishboneIPLib/pcores/plb2wb_bridge_v1_00_a
|
8 |
|
|
OCRAM_LIB_DIR=$(LIB_DIR)/WishboneIPLib/pcores/testram_v1_00_a
|
9 |
|
|
WB_LIB_DIR=$(LIB_DIR)/WishboneIPLib/pcores/wb_conbus_v1_00_a
|
10 |
|
|
|
11 |
|
|
# VHDL compile flags
|
12 |
|
|
VHDL_CFLAGS=-novopt -93 -error -check_synthesis -defercheck -deferSubpgmCheck -rangecheck
|
13 |
|
|
|
14 |
|
|
## Uncomment this, if you are at hochschule pforzheim in a pc-pool.
|
15 |
|
|
# (Check the paths in common/Makefile ->> vmap entries)
|
16 |
|
|
#ENVIRONMENT=HSP
|
17 |
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|
18 |
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|
|
19 |
|
|
ifeq ( $(ENVIRONMENT), "HSP" )
|
20 |
|
|
VMAP= \
|
21 |
|
|
vmap -c; \
|
22 |
|
|
vmap secureip 'c:/Programme/CAEE/ISE_Lib/secureip/'; \
|
23 |
|
|
vmap simprim 'c:/Programme/CAEE/ISE_Lib/simprim/'; \
|
24 |
|
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vmap simprims_ver 'c:/Programme/CAEE/ISE_Lib/simprims_ver/'; \
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25 |
|
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vmap unisim 'c:/Programme/CAEE/ISE_Lib/unisim/'; \
|
26 |
|
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vmap unisims_ver 'c:/Programme/CAEE/ISE_Lib/unisims_ver/'; \
|
27 |
|
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vmap xilinxcorelib 'c:/Programme/CAEE/ISE_Lib/XilinxCoreLib/'; \
|
28 |
|
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vmap xilinxcorelib_ver 'c:/Programme/CAEE/ISE_Lib/XilinxCoreLib_ver/'; \
|
29 |
|
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vmap proc_common_v3_00_a 'c:/Programme/CAEE/EDK_Lib/edk/proc_common_v3_00_a/'; \
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30 |
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vmap plb_v46_v1_04_a 'c:/Programme/CAEE/EDK_Lib/edk/plb_v46_v1_04_a/'; \
|
31 |
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vmap bfm_synch_v1_00_a 'c:/Programme/CAEE/EDK_Lib/edk/bfm_synch_v1_00_a/'; \
|
32 |
|
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vmap plbv46_bfm 'c:/Programme/CAEE/EDK_Lib/edk/plbv46_bfm/'; \
|
33 |
|
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vmap plbv46_master_bfm_v1_00_a 'c:/Programme/CAEE/EDK_Lib/edk/plbv46_master_bfm_v1_00_a/'; \
|
34 |
|
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vmap plbv46_monitor_bfm_v1_00_a 'c:/Programme/CAEE/EDK_Lib/edk/plbv46_monitor_bfm_v1_00_a/'; \
|
35 |
|
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vmap plbv46_slave_bfm_v1_00_a 'c:/Programme/CAEE/EDK_Lib/edk/plbv46_slave_bfm_v1_00_a/'; \
|
36 |
|
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vmap plbv46_slave_single_v1_01_a 'c:/Programme/CAEE/EDK_Lib/edk/plbv46_slave_single_v1_01_a/';
|
37 |
|
|
|
38 |
|
|
else
|
39 |
|
|
VMAP= \
|
40 |
|
|
vmap -c; \
|
41 |
|
|
vmap unisim '/opt/Xilinx/11.1/compxlib/unisim/'; \
|
42 |
|
|
vmap unisims_ver '/opt/Xilinx/11.1/compxlib/unisims_ver/'; \
|
43 |
|
|
vmap proc_common_v3_00_a '/opt/Xilinx/11.1/compxlib/edk/proc_common_v3_00_a/'; \
|
44 |
|
|
vmap plb_v46_v1_04_a '/opt/Xilinx/11.1/compxlib/edk/plb_v46_v1_04_a/'; \
|
45 |
|
|
vmap bfm_synch_v1_00_a '/opt/Xilinx/11.1/compxlib/edk/bfm_synch_v1_00_a/'; \
|
46 |
|
|
vmap plbv46_bfm '/opt/Xilinx/11.1/compxlib/edk/plbv46_bfm/'; \
|
47 |
|
|
vmap plbv46_master_bfm_v1_00_a '/opt/Xilinx/11.1/compxlib/edk/plbv46_master_bfm_v1_00_a/'; \
|
48 |
|
|
vmap plbv46_monitor_bfm_v1_00_a '/opt/Xilinx/11.1/compxlib/edk/plbv46_monitor_bfm_v1_00_a/'; \
|
49 |
|
|
vmap plbv46_slave_bfm_v1_00_a '/opt/Xilinx/11.1/compxlib/edk/plbv46_slave_bfm_v1_00_a/'; \
|
50 |
|
|
vlib work; \
|
51 |
|
|
vmap work work; \
|
52 |
|
|
vlib plb2wb_bridge_v1_00_a; \
|
53 |
|
|
vmap plb2wb_bridge_v1_00_a plb2wb_bridge_v1_00_a;
|
54 |
|
|
endif
|
55 |
|
|
|
56 |
|
|
|
57 |
|
|
###########
|
58 |
|
|
ONCHIP_RAM_TARGET=$(CUR_DIR)/testram_*/testram/_primary.dat
|
59 |
|
|
WB_TARGET=$(CUR_DIR)/wb_conbus_*/wb_conbus_*/_primary.dat
|
60 |
|
|
WORK_TARGET=$(CUR_DIR)/work/system/_primary.dat
|
61 |
|
|
PLB2WB_BRIDGE_TARGET=$(CUR_DIR)/plb2wb_bridge_*/plb2wb_bridge/_primary.dat
|
62 |
|
|
###########
|
63 |
|
|
|
64 |
|
|
|
65 |
|
|
|
66 |
|
|
###########
|
67 |
|
|
PLB2WB_BRIDGE_SRC=$(PLB2WB_LIB_DIR)/hdl/vhdl/*.vhd \
|
68 |
|
|
../testbench/plb2wb_amu_tb.vhd
|
69 |
|
|
|
70 |
|
|
ONCHIP_RAM_SRC=$(OCRAM_LIB_DIR)/hdl/vhdl/testram.vhd
|
71 |
|
|
WB_SRC=$(WB_LIB_DIR)/hdl/verilog/*.v
|
72 |
|
|
###########
|
73 |
|
|
|
74 |
|
|
|
75 |
|
|
|
76 |
|
|
|
77 |
|
|
|
78 |
|
|
WORK_SRC= $(SIM_DIR)/behavioral/mb_plb_wrapper.vhd \
|
79 |
|
|
$(SIM_DIR)/behavioral/plb_bfm_master_32_wrapper.vhd \
|
80 |
|
|
$(SIM_DIR)/behavioral/plb_bfm_monitor_wrapper.vhd \
|
81 |
|
|
$(SIM_DIR)/behavioral/plb_bfm_slave_wrapper.vhd \
|
82 |
|
|
$(SIM_DIR)/behavioral/plb_bfm_synch_wrapper.vhd \
|
83 |
|
|
$(SIM_DIR)/behavioral/system.vhd \
|
84 |
|
|
$(SIM_DIR)/testbench/system_tb.vhd
|
85 |
|
|
|
86 |
|
|
VHDL_BRIDGE_SRC=$(SIM_DIR)/behavioral/plb2wb_bridge_0_wrapper.vhd
|
87 |
|
|
|
88 |
|
|
|
89 |
|
|
#
|
90 |
|
|
# Generate Simulation HDL Files
|
91 |
|
|
# (This is the same than XPS-Gui->Simulation->Generate Simulation HDL Files)
|
92 |
|
|
#
|
93 |
|
|
$(WORK_SRC): $(XPS_PROJ_DIR)/system.mhs
|
94 |
|
|
simgen $(XPS_PROJ_DIR)/system.mhs -lang vhdl \
|
95 |
|
|
-p virtex5 \
|
96 |
|
|
-m beh \
|
97 |
|
|
-od $(XPS_PROJ_DIR)/ \
|
98 |
|
|
-s mti \
|
99 |
|
|
-lp $(LIB_DIR)
|
100 |
|
|
|
101 |
|
|
#
|
102 |
|
|
#
|
103 |
|
|
# Generate the modelsim.ini file and working directory
|
104 |
|
|
# after this, modelsim.ini contains the library mappings
|
105 |
|
|
#
|
106 |
|
|
modelsim.ini:
|
107 |
|
|
$(VMAP)
|
108 |
|
|
|
109 |
|
|
|
110 |
|
|
|
111 |
|
|
#
|
112 |
|
|
# Compile the Bus Functional Model script file
|
113 |
|
|
# transfers.bfl: is written in PLB Bus Functional Language
|
114 |
|
|
# (see $XILINX_EDK/third_party/doc/PlbToolkit.pdf )
|
115 |
|
|
# xilbfc: Bus functional compiler (perl script)
|
116 |
|
|
#
|
117 |
|
|
|
118 |
|
|
transfers.do: transfers.bfl
|
119 |
|
|
xilbfc transfers.bfl
|
120 |
|
|
|
121 |
|
|
#
|
122 |
|
|
# Compile the vhdl-sources with modelsim vhdl compiler
|
123 |
|
|
#
|
124 |
|
|
$(WORK_TARGET): $(WORK_SRC)
|
125 |
|
|
vlib work; \
|
126 |
|
|
vmap work work; \
|
127 |
|
|
vlog -novopt -93 -work work "../behavioral/wb_conbus_0_wrapper.v"; \
|
128 |
|
|
vcom $(VHDL_CFLAGS) -work work \
|
129 |
|
|
"../behavioral/onchip_ram_0_wrapper.vhd" \
|
130 |
|
|
"../behavioral/onchip_ram_1_wrapper.vhd" \
|
131 |
|
|
"../behavioral/onchip_ram_2_wrapper.vhd" \
|
132 |
|
|
"../behavioral/onchip_ram_3_wrapper.vhd" \
|
133 |
|
|
"../behavioral/mb_plb_wrapper.vhd" \
|
134 |
|
|
"../behavioral/plb_bfm_master_32_wrapper.vhd" \
|
135 |
|
|
"../behavioral/plb_bfm_master_64_wrapper.vhd" \
|
136 |
|
|
"../behavioral/plb_bfm_master_128_wrapper.vhd" \
|
137 |
|
|
"../behavioral/plb_bfm_monitor_wrapper.vhd" \
|
138 |
|
|
"../behavioral/plb_bfm_slave_wrapper.vhd" \
|
139 |
|
|
"../behavioral/plb_bfm_synch_wrapper.vhd" \
|
140 |
|
|
"../behavioral/plb2wb_bridge_0_wrapper.vhd" \
|
141 |
|
|
"../behavioral/system.vhd" \
|
142 |
|
|
"../testbench/system_tb.vhd"
|
143 |
|
|
|
144 |
|
|
|
145 |
|
|
$(PLB2WB_BRIDGE_TARGET): $(PLB2WB_BRIDGE_SRC)
|
146 |
|
|
vlib plb2wb_bridge_v1_00_a;
|
147 |
|
|
vmap plb2wb_bridge_v1_00_a plb2wb_bridge_v1_00_a;
|
148 |
|
|
vcom $(VHDL_CFLAGS) -work plb2wb_bridge_v1_00_a \
|
149 |
|
|
"$(PLB2WB_LIB_DIR)/hdl/vhdl/plb2wb_pkg.vhd" \
|
150 |
|
|
"$(PLB2WB_LIB_DIR)/hdl/vhdl/plb2wb_short_impulse.vhd" \
|
151 |
|
|
"$(PLB2WB_LIB_DIR)/hdl/vhdl/fifo_adr_cc_4.vhd" \
|
152 |
|
|
"$(PLB2WB_LIB_DIR)/hdl/vhdl/fifo_adr_ic_4.vhd" \
|
153 |
|
|
"$(PLB2WB_LIB_DIR)/hdl/vhdl/fifo_adr_cc_3.vhd" \
|
154 |
|
|
"$(PLB2WB_LIB_DIR)/hdl/vhdl/fifo_adr_ic_3.vhd" \
|
155 |
|
|
"$(PLB2WB_LIB_DIR)/hdl/vhdl/fifo_adr_cc_2.vhd" \
|
156 |
|
|
"$(PLB2WB_LIB_DIR)/hdl/vhdl/fifo_adr_ic_2.vhd" \
|
157 |
|
|
"$(PLB2WB_LIB_DIR)/hdl/vhdl/fifo_adr_cc_1.vhd" \
|
158 |
|
|
"$(PLB2WB_LIB_DIR)/hdl/vhdl/fifo_adr_ic_1.vhd" \
|
159 |
|
|
"$(PLB2WB_LIB_DIR)/hdl/vhdl/fifo_adr.vhd" \
|
160 |
|
|
"$(PLB2WB_LIB_DIR)/hdl/vhdl/fifo_rdat_cc_32.vhd" \
|
161 |
|
|
"$(PLB2WB_LIB_DIR)/hdl/vhdl/fifo_rdat_ic_32.vhd" \
|
162 |
|
|
"$(PLB2WB_LIB_DIR)/hdl/vhdl/fifo_rdat.vhd" \
|
163 |
|
|
"$(PLB2WB_LIB_DIR)/hdl/vhdl/fifo_wdat_cc_32.vhd" \
|
164 |
|
|
"$(PLB2WB_LIB_DIR)/hdl/vhdl/fifo_wdat_ic_32.vhd" \
|
165 |
|
|
"$(PLB2WB_LIB_DIR)/hdl/vhdl/fifo_wdat.vhd" \
|
166 |
|
|
"$(PLB2WB_LIB_DIR)/hdl/vhdl/fifo_stat2plb.vhd" \
|
167 |
|
|
"$(PLB2WB_LIB_DIR)/hdl/vhdl/fifo_stat2plb_ic_4.vhd" \
|
168 |
|
|
"$(PLB2WB_LIB_DIR)/hdl/vhdl/fifo_stat2plb_cc_4.vhd" \
|
169 |
|
|
"$(PLB2WB_LIB_DIR)/hdl/vhdl/fifo_stat2plb_ic_3.vhd" \
|
170 |
|
|
"$(PLB2WB_LIB_DIR)/hdl/vhdl/fifo_stat2plb_cc_3.vhd" \
|
171 |
|
|
"$(PLB2WB_LIB_DIR)/hdl/vhdl/fifo_stat2plb_ic_2.vhd" \
|
172 |
|
|
"$(PLB2WB_LIB_DIR)/hdl/vhdl/fifo_stat2plb_cc_2.vhd" \
|
173 |
|
|
"$(PLB2WB_LIB_DIR)/hdl/vhdl/fifo_stat2plb_ic_1.vhd" \
|
174 |
|
|
"$(PLB2WB_LIB_DIR)/hdl/vhdl/fifo_stat2plb_cc_1.vhd" \
|
175 |
|
|
"$(PLB2WB_LIB_DIR)/hdl/vhdl/fifo_stat2wb.vhd" \
|
176 |
|
|
"$(PLB2WB_LIB_DIR)/hdl/vhdl/fifo_stat2wb_ic.vhd" \
|
177 |
|
|
"$(PLB2WB_LIB_DIR)/hdl/vhdl/fifo_stat2wb_cc.vhd" \
|
178 |
|
|
"$(PLB2WB_LIB_DIR)/hdl/vhdl/plb2wb_fifo.vhd" \
|
179 |
|
|
"$(PLB2WB_LIB_DIR)/hdl/vhdl/plb2wb_stu.vhd" \
|
180 |
|
|
"$(PLB2WB_LIB_DIR)/hdl/vhdl/plb2wb_tcu.vhd" \
|
181 |
|
|
"$(PLB2WB_LIB_DIR)/hdl/vhdl/plb2wb_amu.vhd" \
|
182 |
|
|
"$(PLB2WB_LIB_DIR)/hdl/vhdl/plb2wb_rbuf.vhd" \
|
183 |
|
|
"$(PLB2WB_LIB_DIR)/hdl/vhdl/plb2wb_wbuf.vhd" \
|
184 |
|
|
"$(PLB2WB_LIB_DIR)/hdl/vhdl/plb2wb_bridge.vhd"
|
185 |
|
|
|
186 |
|
|
|
187 |
|
|
|
188 |
|
|
$(ONCHIP_RAM_TARGET): $(ONCHIP_RAM_SRC)
|
189 |
|
|
vlib testram_v1_00_a;
|
190 |
|
|
vmap testram_v1_00_a testram_v1_00_a;
|
191 |
|
|
vcom $(VHDL_CFLAGS) -work testram_v1_00_a $(OCRAM_LIB_DIR)/hdl/vhdl/testram.vhd
|
192 |
|
|
|
193 |
|
|
|
194 |
|
|
$(WB_TARGET): $(WB_SRC)
|
195 |
|
|
vlib wb_conbus_v1_00_a;
|
196 |
|
|
vmap wb_conbus_v1_00_a wb_conbus_v1_00_a;
|
197 |
|
|
vlog -novopt -93 -work wb_conbus_v1_00_a "$(WB_LIB_DIR)/hdl/verilog/wb_conbus_arb.v" \
|
198 |
|
|
"$(WB_LIB_DIR)/hdl/verilog/wb_conbus_top.v" \
|
199 |
|
|
"$(WB_LIB_DIR)/hdl/verilog/wb_conbus_wrapper.v"
|
200 |
|
|
|
201 |
|
|
|
202 |
|
|
|
203 |
|
|
compile: modelsim.ini $(ONCHIP_RAM_TARGET) $(WORK_TARGET) $(PLB2WB_BRIDGE_TARGET) $(WB_TARGET)
|
204 |
|
|
|
205 |
|
|
sim: modelsim.ini transfers.do $(ONCHIP_RAM_TARGET) $(WORK_TARGET) $(PLB2WB_BRIDGE_TARGET) $(WB_TARGET)
|
206 |
|
|
vsim -quiet -l simulation.log -do sim.do
|
207 |
|
|
|
208 |
|
|
|
209 |
|
|
sim_fifo: ./plb2wb_bridge_*/plb2wb_bridge/_primary.dat
|
210 |
|
|
vsim -quiet -do sim_fifo.do
|
211 |
|
|
|
212 |
|
|
sim_amu : ./plb2wb_bridge_*/plb2wb_bridge/_primary.dat
|
213 |
|
|
vsim -quiet -do sim_amu.do
|
214 |
|
|
|
215 |
|
|
sim_clk_trans: ./plb2wb_bridge_*/plb2wb_bridge/_primary.dat
|
216 |
|
|
vsim -quiet -do sim_clk_trans.do
|
217 |
|
|
|
218 |
|
|
clean:
|
219 |
|
|
rm -rf work \
|
220 |
|
|
simgen.log \
|
221 |
|
|
simgen.opt \
|
222 |
|
|
transcript \
|
223 |
|
|
vsim.wlf \
|
224 |
|
|
modelsim.ini \
|
225 |
|
|
../behavioral \
|
226 |
|
|
xilbfc.log \
|
227 |
|
|
plb2wb_bridge_v1_00_a \
|
228 |
|
|
wb_conbus_v1_00_a \
|
229 |
|
|
testram_v1_00_a \
|
230 |
|
|
wb_conbus_v1_00_a \
|
231 |
|
|
bfm_synch_v1_00_a \
|
232 |
|
|
plb_v46_v1_04_a \
|
233 |
|
|
plbv46_bfm \
|
234 |
|
|
plbv46_master_bfm_v1_00_a \
|
235 |
|
|
plbv46_monitor_bfm_v1_00_a \
|
236 |
|
|
plbv46_slave_bfm_v1_00_a \
|
237 |
|
|
plbv46_slave_single_v1_01_a \
|
238 |
|
|
proc_common_v3_00_a \
|
239 |
|
|
modelsim_proj.cr.mti \
|
240 |
|
|
transfers.do
|