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SIM_DIR=$(shell pwd)
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XPS_PROJ_DIR=$(SIM_DIR)/..
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SIM_BIN_DIR=$(SIM_DIR)/sim_bin
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COMMON_DIR=$(SIM_DIR)/../../common
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LOG_DIR=$(SIM_DIR)/log
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PLB_BFM_SETUP_DIR=$(SIM_DIR)/../../plb_bfm_setup
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include $(COMMON_DIR)/Makefile
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all: sim
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TEST_CASES += test_cases/simple_read_write
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WORK_TARGET=$(SIM_BIN_DIR)/work/system/_primary.dat
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###
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#
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# note: WORK_TARGET is defined some lines above, the rest in ../../common/Makefile
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#
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COMPILE_COMPONENTS=$(TESTRAM_TARGET) $(PLB2WB_BRIDGE_TARGET) $(WB_TARGET) $(PLB_BFM_TARGET) $(WORK_TARGET)
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#
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# Generate Simulation HDL Files
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# (This is the same than XPS-Gui->Simulation->Generate Simulation HDL Files)
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#
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$(SIM_DIR)/behavioral: $(XPS_PROJ_DIR)/system.mhs
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@mkdir -p $(LOG_DIR)
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simgen $(XPS_PROJ_DIR)/system.mhs -lang vhdl \
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-p virtex5 \
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-m beh \
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-od $(XPS_PROJ_DIR)/ \
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-s mti \
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-lp $(LIB_DIR) \
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-log $(LOG_DIR)/simgen
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@mv simgen.opt log # there is no simgen-flag for this!
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# PLB_BFM_TARGET=$(SIM_BIN_DIR)/plbv46_bfm/system/_primary.dat
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# #BFM_SOURCE=$() TODO
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# $(PLB_BFM_TARGET):
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# cd $(SIM_BIN_DIR); \
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# vlib plbv46_bfm; \
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# vmap plbv46_bfm plbv46_bfm; \
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# vlib plbv46_master_bfm_v1_00_a; \
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# vmap plbv46_master_bfm_v1_00_a plbv46_master_bfm_v1_00_a; \
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# vlib plbv46_monitor_bfm_v1_00_a; \
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# vmap plbv46_monitor_bfm_v1_00_a plbv46_monitor_bfm_v1_00_a; \
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# vlib plbv46_slave_bfm_v1_00_a; \
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# vmap plbv46_slave_bfm_v1_00_a plbv46_slave_bfm_v1_00_a; \
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# vcom $(VHDL_CFLAGS) -work plbv46_bfm \
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# "$(PLB_BFM_SETUP_DIR)/plb_dcl_128.vhd"; \
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# vcom $(VHDL_CFLAGS) -work plbv46_master_bfm_v1_00_a \
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# "$(PLB_BFM_LIB_DIR)/pcores/plbv46_master_bfm_v1_00_a/hdl/vhdl/plbv46_master_bfm.vhd" ; \
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# vcom $(VHDL_CFLAGS) -work plbv46_monitor_bfm_v1_00_a \
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# "$(PLB_BFM_LIB_DIR)/pcores/plbv46_monitor_bfm_v1_00_a/hdl/vhdl/plbv46_monitor_bfm.vhd";\
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# vcom $(VHDL_CFLAGS) -work plbv46_slave_bfm_v1_00_a \
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# "$(PLB_BFM_LIB_DIR)/pcores/plbv46_slave_bfm_v1_00_a/hdl/vhdl/plbv46_slave_bfm.vhd";
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$(WORK_TARGET): $(SIM_DIR)/behavioral $(SIM_BIN_DIR)/../testbench/system_tb.vhd
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cd $(SIM_BIN_DIR); \
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vlib work; \
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vmap work work; \
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vlog -novopt -93 -work work "../behavioral/wb_conbus_0_wrapper.v"; \
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vcom $(VHDL_CFLAGS) -work work \
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"../behavioral/onchip_ram_0_wrapper.vhd" \
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"../behavioral/onchip_ram_1_wrapper.vhd" \
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"../behavioral/onchip_ram_2_wrapper.vhd" \
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"../behavioral/onchip_ram_3_wrapper.vhd" \
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"../behavioral/mb_plb_wrapper.vhd" \
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"../behavioral/plb_bfm_master_32_wrapper.vhd" \
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"../behavioral/plb_bfm_master_64_wrapper.vhd" \
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"../behavioral/plb_bfm_master_128_wrapper.vhd" \
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"../behavioral/plb_bfm_monitor_wrapper.vhd" \
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"../behavioral/plb_bfm_slave_wrapper.vhd" \
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"../behavioral/plb_bfm_synch_wrapper.vhd" \
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"../behavioral/plb2wb_bridge_0_wrapper.vhd" \
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"../behavioral/system.vhd" \
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"../testbench/system_tb.vhd"
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compile: $(SIM_BIN_DIR)/modelsim.ini $(COMPILE_COMPONENTS)
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clean:
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rm -rf \
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$(SIM_DIR)/behavioral \
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$(SIM_BIN_DIR) \
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$(LOG_DIR)
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