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Subversion Repositories plb2wbbridge

[/] [plb2wbbridge/] [trunk/] [systems/] [test_system_sim/] [wb_irqs/] [system.mhs] - Blame information for rev 2

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# ##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 11.4 Build EDK_LS4.68
# Fri Mar  5 18:02:26 2010
# Target Board:  Xilinx Virtex 5 ML501 Evaluation Platform Rev 1
# Family:    virtex5
# Device:    xc5vlx50
# Package:   ff676
# Speed Grade:  -1
# Processor number: 1
# Processor 1: microblaze_0
# System clock frequency: 125.0
# Debug Interface: On-Chip HW Debug Module
# ##############################################################################
 PARAMETER VERSION = 2.1.0
 
 
 PORT sys_clk_pin = clk_100MHz, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
 PORT sys_rst_pin = sys_rst_s, DIR = I, SIGIS = RST, RST_POLARITY = 1
 PORT to_synch_in_pin = synch_in, DIR = I, VEC = [0:31]
 PORT from_synch_out_pin = synch_out, DIR = O, VEC = [0:31]
 PORT wb_clk_pin = wb_clk, DIR = I, SIGIS = CLK
 PORT wb_rst_pin = wb_rst, DIR = I, SIGIS = RST
 PORT PLB2WB_IRQ_pin = PLB2WB_IRQ, DIR = O
 PORT wb_pic_int_i_pin = wb_pic_int_i, DIR = I, VEC = [3:0]
 
 
BEGIN plb_v46
 PARAMETER INSTANCE = mb_plb
 PARAMETER HW_VER = 1.04.a
 PARAMETER C_EXT_RESET_HIGH = 1
 PARAMETER C_DCR_INTFCE = 1
 PARAMETER C_BASEADDR = 0b0000000000
 PARAMETER C_HIGHADDR = 0b1111111111
 PORT PLB_Clk = clk_100MHz
 PORT SYS_Rst = sys_rst_s
END
 
BEGIN plbv46_master_bfm
 PARAMETER INSTANCE = plb_bfm_master_32
 PARAMETER HW_VER = 1.00.a
 PARAMETER PLB_MASTER_SIZE = 0b10
 PARAMETER PLB_MASTER_NUM = 0b0000
 PARAMETER C_MPLB_NATIVE_DWIDTH = 128
 PARAMETER PLB_MASTER_ADDR_HI_0 = 0xffffffff
 BUS_INTERFACE MPLB = mb_plb
 PORT SYNCH_OUT = bfm_synch_out_0
 PORT SYNCH_IN = synch_in
END
 
BEGIN plbv46_monitor_bfm
 PARAMETER INSTANCE = plb_bfm_monitor
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE MON_PLB = mb_plb
 PORT SYNCH_OUT = bfm_synch_out_1
 PORT SYNCH_IN = synch_in
END
 
BEGIN bfm_synch
 PARAMETER INSTANCE = plb_bfm_synch
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_NUM_SYNCH = 2
 PORT TO_SYNCH_IN = synch_out
 PORT FROM_SYNCH_OUT = bfm_synch_out_0 & bfm_synch_out_1
END
 
BEGIN plb2wb_bridge
 PARAMETER INSTANCE = plb2wb_bridge_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_BASEADDR = 0xf0000000
 PARAMETER C_HIGHADDR = 0xf7ffffff
 PARAMETER WB_ADR_OFFSET = 0xf0000000
 PARAMETER WB_ADR_OFFSET_NEG = 1
 PARAMETER SYNCHRONY = false
 PARAMETER C_STATUS_BASEADDR = 0x00010000
 PARAMETER C_STATUS_HIGHADDR = 0x0001FFFF
 PARAMETER WB_PIC_INTS = 4
 BUS_INTERFACE SPLB = mb_plb
 BUS_INTERFACE MWB = wb_conbus_0
 PORT SPLB_Clk = clk_100MHz
 PORT wb_clk_i = wb_clk
 PORT wb_rst_i = wb_rst
 PORT PLB2WB_IRQ = PLB2WB_IRQ
 PORT wb_pic_int_i = wb_pic_int_i
END
 
BEGIN wb_conbus
 PARAMETER INSTANCE = wb_conbus_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER wb_s0_addr = 0x00
 PARAMETER wb_s27_addr_w = 8
 PARAMETER wb_s1_addr = 0x01
 PARAMETER wb_s2_addr = 0x02
 PARAMETER wb_s3_addr = 0x03
 PARAMETER wb_s4_addr = 0x04
 PARAMETER wb_s5_addr = 0x05
 PARAMETER wb_s6_addr = 0x06
 PARAMETER wb_s7_addr = 0x07
 PARAMETER wb_s0_addr_w = 8
 PARAMETER wb_s1_addr_w = 8
 PORT wb_rst_i = wb_rst
 PORT wb_clk_i = wb_clk
END
 
BEGIN testram
 PARAMETER INSTANCE = onchip_ram_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER RD_DELAY = 0
 PARAMETER WR_DELAY = 0
 PARAMETER WITH_ERR_OR_RTY = 0b10
 PARAMETER ERR_RTY_INTERVAL = 5
 BUS_INTERFACE SWB = wb_conbus_0
 PORT wb_rst_i = wb_rst
 PORT wb_clk_i = wb_clk
END
 

Line No.	Rev	Author	Line
1	2	feddischso
2			`# ##############################################################################`
3			`# Created by Base System Builder Wizard for Xilinx EDK 11.4 Build EDK_LS4.68`
4			`# Fri Mar 5 18:02:26 2010`
5			`# Target Board: Xilinx Virtex 5 ML501 Evaluation Platform Rev 1`
6			`# Family: virtex5`
7			`# Device: xc5vlx50`
8			`# Package: ff676`
9			`# Speed Grade: -1`
10			`# Processor number: 1`
11			`# Processor 1: microblaze_0`
12			`# System clock frequency: 125.0`
13			`# Debug Interface: On-Chip HW Debug Module`
14			`# ##############################################################################`
15			`PARAMETER VERSION = 2.1.0`
16
17
18			`PORT sys_clk_pin = clk_100MHz, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000`
19			`PORT sys_rst_pin = sys_rst_s, DIR = I, SIGIS = RST, RST_POLARITY = 1`
20			`PORT to_synch_in_pin = synch_in, DIR = I, VEC = [0:31]`
21			`PORT from_synch_out_pin = synch_out, DIR = O, VEC = [0:31]`
22			`PORT wb_clk_pin = wb_clk, DIR = I, SIGIS = CLK`
23			`PORT wb_rst_pin = wb_rst, DIR = I, SIGIS = RST`
24			`PORT PLB2WB_IRQ_pin = PLB2WB_IRQ, DIR = O`
25			`PORT wb_pic_int_i_pin = wb_pic_int_i, DIR = I, VEC = [3:0]`
26
27
28			`BEGIN plb_v46`
29			`PARAMETER INSTANCE = mb_plb`
30			`PARAMETER HW_VER = 1.04.a`
31			`PARAMETER C_EXT_RESET_HIGH = 1`
32			`PARAMETER C_DCR_INTFCE = 1`
33			`PARAMETER C_BASEADDR = 0b0000000000`
34			`PARAMETER C_HIGHADDR = 0b1111111111`
35			`PORT PLB_Clk = clk_100MHz`
36			`PORT SYS_Rst = sys_rst_s`
37			`END`
38
39			`BEGIN plbv46_master_bfm`
40			`PARAMETER INSTANCE = plb_bfm_master_32`
41			`PARAMETER HW_VER = 1.00.a`
42			`PARAMETER PLB_MASTER_SIZE = 0b10`
43			`PARAMETER PLB_MASTER_NUM = 0b0000`
44			`PARAMETER C_MPLB_NATIVE_DWIDTH = 128`
45			`PARAMETER PLB_MASTER_ADDR_HI_0 = 0xffffffff`
46			`BUS_INTERFACE MPLB = mb_plb`
47			`PORT SYNCH_OUT = bfm_synch_out_0`
48			`PORT SYNCH_IN = synch_in`
49			`END`
50
51			`BEGIN plbv46_monitor_bfm`
52			`PARAMETER INSTANCE = plb_bfm_monitor`
53			`PARAMETER HW_VER = 1.00.a`
54			`BUS_INTERFACE MON_PLB = mb_plb`
55			`PORT SYNCH_OUT = bfm_synch_out_1`
56			`PORT SYNCH_IN = synch_in`
57			`END`
58
59			`BEGIN bfm_synch`
60			`PARAMETER INSTANCE = plb_bfm_synch`
61			`PARAMETER HW_VER = 1.00.a`
62			`PARAMETER C_NUM_SYNCH = 2`
63			`PORT TO_SYNCH_IN = synch_out`
64			`PORT FROM_SYNCH_OUT = bfm_synch_out_0 & bfm_synch_out_1`
65			`END`
66
67			`BEGIN plb2wb_bridge`
68			`PARAMETER INSTANCE = plb2wb_bridge_0`
69			`PARAMETER HW_VER = 1.00.a`
70			`PARAMETER C_BASEADDR = 0xf0000000`
71			`PARAMETER C_HIGHADDR = 0xf7ffffff`
72			`PARAMETER WB_ADR_OFFSET = 0xf0000000`
73			`PARAMETER WB_ADR_OFFSET_NEG = 1`
74			`PARAMETER SYNCHRONY = false`
75			`PARAMETER C_STATUS_BASEADDR = 0x00010000`
76			`PARAMETER C_STATUS_HIGHADDR = 0x0001FFFF`
77			`PARAMETER WB_PIC_INTS = 4`
78			`BUS_INTERFACE SPLB = mb_plb`
79			`BUS_INTERFACE MWB = wb_conbus_0`
80			`PORT SPLB_Clk = clk_100MHz`
81			`PORT wb_clk_i = wb_clk`
82			`PORT wb_rst_i = wb_rst`
83			`PORT PLB2WB_IRQ = PLB2WB_IRQ`
84			`PORT wb_pic_int_i = wb_pic_int_i`
85			`END`
86
87			`BEGIN wb_conbus`
88			`PARAMETER INSTANCE = wb_conbus_0`
89			`PARAMETER HW_VER = 1.00.a`
90			`PARAMETER wb_s0_addr = 0x00`
91			`PARAMETER wb_s27_addr_w = 8`
92			`PARAMETER wb_s1_addr = 0x01`
93			`PARAMETER wb_s2_addr = 0x02`
94			`PARAMETER wb_s3_addr = 0x03`
95			`PARAMETER wb_s4_addr = 0x04`
96			`PARAMETER wb_s5_addr = 0x05`
97			`PARAMETER wb_s6_addr = 0x06`
98			`PARAMETER wb_s7_addr = 0x07`
99			`PARAMETER wb_s0_addr_w = 8`
100			`PARAMETER wb_s1_addr_w = 8`
101			`PORT wb_rst_i = wb_rst`
102			`PORT wb_clk_i = wb_clk`
103			`END`
104
105			`BEGIN testram`
106			`PARAMETER INSTANCE = onchip_ram_0`
107			`PARAMETER HW_VER = 1.00.a`
108			`PARAMETER RD_DELAY = 0`
109			`PARAMETER WR_DELAY = 0`
110			`PARAMETER WITH_ERR_OR_RTY = 0b10`
111			`PARAMETER ERR_RTY_INTERVAL = 5`
112			`BUS_INTERFACE SWB = wb_conbus_0`
113			`PORT wb_rst_i = wb_rst`
114			`PORT wb_clk_i = wb_clk`
115			`END`
116

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Subversion Repositories plb2wbbridge

[/] [plb2wbbridge/] [trunk/] [systems/] [test_system_sim/] [wb_irqs/] [system.mhs] - Blame information for rev 2