URL https://opencores.org/ocsvn/plb2wbbridge/plb2wbbridge/trunk

Subversion Repositories plb2wbbridge

[/] [plb2wbbridge/] [trunk/] [systems/] [test_system_sim/] [wb_irqs/] [system.xmp] - Blame information for rev 2

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#Please do not modify this file by hand
XmpVersion: 11.4
VerMgmt: 11.4
IntStyle: default
ModuleSearchPath: ../../EDK_Libs/
MHS File: system.mhs
MSS File: system.mss
Architecture: virtex5
Device: xc5vlx50
Package: ff676
SpeedGrade: -1
UserCmd1:
UserCmd1Type: 0
UserCmd2:
UserCmd2Type: 0
GenSimTB: 0
SdkExportBmmBit: 1
SdkExportDir: SDK/SDK_Export
InsertNoPads: 0
WarnForEAArch: 1
HdlLang: VHDL
SimModel: BEHAVIORAL
UcfFile: data/system.ucf
EnableParTimingError: 1
ShowLicenseDialog: 1

Line No.	Rev	Author	Line
1	2	feddischso	`#Please do not modify this file by hand`
2			`XmpVersion: 11.4`
3			`VerMgmt: 11.4`
4			`IntStyle: default`
5			`ModuleSearchPath: ../../EDK_Libs/`
6			`MHS File: system.mhs`
7			`MSS File: system.mss`
8			`Architecture: virtex5`
9			`Device: xc5vlx50`
10			`Package: ff676`
11			`SpeedGrade: -1`
12			`UserCmd1:`
13			`UserCmd1Type: 0`
14			`UserCmd2:`
15			`UserCmd2Type: 0`
16			`GenSimTB: 0`
17			`SdkExportBmmBit: 1`
18			`SdkExportDir: SDK/SDK_Export`
19			`InsertNoPads: 0`
20			`WarnForEAArch: 1`
21			`HdlLang: VHDL`
22			`SimModel: BEHAVIORAL`
23			`UcfFile: data/system.ucf`
24			`EnableParTimingError: 1`
25			`ShowLicenseDialog: 1`

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Subversion Repositories plb2wbbridge

[/] [plb2wbbridge/] [trunk/] [systems/] [test_system_sim/] [wb_irqs/] [system.xmp] - Blame information for rev 2