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----------------------------------------------------------------------
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---- ----
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---- PlTbUtils Testbench Example 2 ----
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---- ----
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---- This file is part of the PlTbUtils project ----
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---- http://opencores.org/project,pltbutils ----
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---- ----
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---- Description: ----
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---- PlTbUtils is a collection of functions, procedures and ----
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---- components for easily creating stimuli and checking response ----
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---- in automatic self-checking testbenches. ----
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---- ----
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---- This file is an example which demonstrates how PlTbUtils ----
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---- can be used. ----
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---- ----
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---- ----
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---- To Do: ----
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---- - ----
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---- ----
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---- Author(s): ----
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---- - Per Larsson, pela@opencores.org ----
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---- ----
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----------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2013-2014 Authors and OPENCORES.ORG ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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----------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.pltbutils_func_pkg.all;
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use work.pltbutils_comp_pkg.all;
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entity tb_example2 is
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generic (
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G_WIDTH : integer := 8;
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G_CLK_PERIOD : time := 10 ns;
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G_DISABLE_BUGS : integer range 0 to 1 := 0
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);
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end entity tb_example2;
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architecture bhv of tb_example2 is
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-- Simulation status- and control signals
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-- for accessing .stop_sim and for viewing in waveform window
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signal pltbs : pltbs_t := C_PLTBS_INIT;
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-- DUT stimuli and response signals
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signal clk : std_logic;
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signal rst : std_logic;
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signal carry_in : std_logic;
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signal x : std_logic_vector(G_WIDTH-1 downto 0);
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signal y : std_logic_vector(G_WIDTH-1 downto 0);
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signal sum : std_logic_vector(G_WIDTH-1 downto 0);
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signal carry_out : std_logic;
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begin
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dut0 : entity work.dut_example
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generic map (
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G_WIDTH => G_WIDTH,
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G_DISABLE_BUGS => G_DISABLE_BUGS
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)
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port map (
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clk_i => clk,
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rst_i => rst,
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carry_i => carry_in,
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x_i => x,
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y_i => y,
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sum_o => sum,
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carry_o => carry_out
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);
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clkgen0 : pltbutils_clkgen
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generic map(
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G_PERIOD => G_CLK_PERIOD
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)
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port map(
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clk_o => clk,
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stop_sim_i => pltbs.stop_sim
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);
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tc0 : entity work.tc_example2
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generic map (
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G_WIDTH => G_WIDTH,
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G_DISABLE_BUGS => G_DISABLE_BUGS
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)
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port map(
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pltbs => pltbs,
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clk => clk,
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rst => rst,
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carry_in => carry_in,
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x => x,
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y => y,
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sum => sum,
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carry_out => carry_out
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);
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end architecture bhv;
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