OpenCores
URL https://opencores.org/ocsvn/pltbutils/pltbutils/trunk

Subversion Repositories pltbutils

[/] [pltbutils/] [branches/] [dev0007/] [examples/] [vhdl/] [tb_example2/] [tc_example2.vhd] - Blame information for rev 65

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 pela
----------------------------------------------------------------------
2
----                                                              ----
3
---- PlTbUtils Example Testcase Entity for Example Testbench      ----
4
----                                                              ----
5
---- This file is part of the PlTbUtils project                   ----
6
---- http://opencores.org/project,pltbutils                       ----
7
----                                                              ----
8
---- Description:                                                 ----
9
---- PlTbUtils is a collection of functions, procedures and       ----
10
---- components for easily creating stimuli and checking response ----
11
---- in automatic self-checking testbenches.                      ----
12
----                                                              ----
13
---- This file is an example which demonstrates how PlTbUtils     ----
14
---- can be used.                                                 ----
15
----                                                              ----
16
----                                                              ----
17
---- To Do:                                                       ----
18
---- -                                                            ----
19
----                                                              ----
20
---- Author(s):                                                   ----
21
---- - Per Larsson, pela@opencores.org                            ----
22
----                                                              ----
23
----------------------------------------------------------------------
24
----                                                              ----
25
---- Copyright (C) 2013 Authors and OPENCORES.ORG                 ----
26
----                                                              ----
27
---- This source file may be used and distributed without         ----
28
---- restriction provided that this copyright statement is not    ----
29
---- removed from the file and that any derivative work contains  ----
30
---- the original copyright notice and the associated disclaimer. ----
31
----                                                              ----
32
---- This source file is free software; you can redistribute it   ----
33
---- and/or modify it under the terms of the GNU Lesser General   ----
34
---- Public License as published by the Free Software Foundation; ----
35
---- either version 2.1 of the License, or (at your option) any   ----
36
---- later version.                                               ----
37
----                                                              ----
38
---- This source is distributed in the hope that it will be       ----
39
---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
40
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
41
---- PURPOSE. See the GNU Lesser General Public License for more  ----
42
---- details.                                                     ----
43
----                                                              ----
44
---- You should have received a copy of the GNU Lesser General    ----
45
---- Public License along with this source; if not, download it   ----
46
---- from http://www.opencores.org/lgpl.shtml                     ----
47
----                                                              ----
48
----------------------------------------------------------------------
49
library ieee;
50
use ieee.std_logic_1164.all;
51 40 pela
use work.pltbutils_func_pkg.all;
52 2 pela
 
53 65 pela
entity tc_example2 is
54 2 pela
  generic (
55 15 pela
    G_WIDTH         : integer := 8;
56
    G_DISABLE_BUGS  : integer range 0 to 1 := 0
57 2 pela
  );
58
  port (
59 40 pela
    pltbs           : out pltbs_t;
60 2 pela
    clk             : in  std_logic;
61
    rst             : out std_logic;
62
    carry_in        : out std_logic;
63
    x               : out std_logic_vector(G_WIDTH-1 downto 0);
64
    y               : out std_logic_vector(G_WIDTH-1 downto 0);
65
    sum             : in  std_logic_vector(G_WIDTH-1 downto 0);
66
    carry_out       : in  std_logic
67
  );
68 65 pela
end entity tc_example2;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.