OpenCores
URL https://opencores.org/ocsvn/pltbutils/pltbutils/trunk

Subversion Repositories pltbutils

[/] [pltbutils/] [branches/] [dev_beta0002/] [examples/] [vhdl/] [tb_example2/] [tc1.vhd] - Blame information for rev 15

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 pela
----------------------------------------------------------------------
2
----                                                              ----
3
---- PlTbUtils Example Testcase Architecture for                  ----
4
---- Example Testbench                                            ----
5
----                                                              ----
6
---- This file is part of the PlTbUtils project                   ----
7
---- http://opencores.org/project,pltbutils                       ----
8
----                                                              ----
9
---- Description:                                                  ----
10
---- PlTbUtils is a collection of functions, procedures and       ----
11
---- components for easily creating stimuli and checking response ----
12
---- in automatic self-checking testbenches.                      ----
13
----                                                              ----
14
---- This file is a template, which can be used as a base when    ----
15
---- testbenches which use PlTbUtils.                             ----
16
---- Copy this file to your preferred location and rename the     ----
17
---- copied file and its contents, by replacing the word          ---- 
18
---- "template" with a name for your design.                      ----
19
---- Also remove informative comments enclosed in < ... > .       ----
20
----                                                              ----
21
----                                                              ----
22
---- To Do:                                                       ----
23
---- -                                                            ----
24
----                                                              ----
25
---- Author(s):                                                   ----
26
---- - Per Larsson, pela@opencores.org                            ----
27
----                                                              ----
28
----------------------------------------------------------------------
29
----                                                              ----
30
---- Copyright (C) 2013 Authors and OPENCORES.ORG                 ----
31
----                                                              ----
32
---- This source file may be used and distributed without         ----
33
---- restriction provided that this copyright statement is not    ----
34
---- removed from the file and that any derivative work contains  ----
35
---- the original copyright notice and the associated disclaimer. ----
36
----                                                              ----
37
---- This source file is free software; you can redistribute it   ----
38
---- and/or modify it under the terms of the GNU Lesser General   ----
39
---- Public License as published by the Free Software Foundation; ----
40
---- either version 2.1 of the License, or (at your option) any   ----
41
---- later version.                                               ----
42
----                                                              ----
43
---- This source is distributed in the hope that it will be       ----
44
---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
45
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
46
---- PURPOSE. See the GNU Lesser General Public License for more  ----
47
---- details.                                                     ----
48
----                                                              ----
49
---- You should have received a copy of the GNU Lesser General    ----
50
---- Public License along with this source; if not, download it   ----
51
---- from http://www.opencores.org/lgpl.shtml                     ----
52
----                                                              ----
53
----------------------------------------------------------------------
54
library ieee;
55
use ieee.std_logic_1164.all;
56
use ieee.numeric_std.all;
57
use work.pltbutils_func_pkg.all;
58
 
59
-- NOTE: The purpose of the following code is to demonstrate some of the 
60
-- features in PlTbUtils, not to do a thorough verification.
61
architecture tc1 of tc_example is
62
begin
63
  p_tc1 : process
64
  begin
65
    startsim("tc1", pltbutils_sc);
66
    rst         <= '1';
67
    carry_in    <= '0';
68
    x           <= (others => '0');
69
    y           <= (others => '0');
70
 
71
    testname(1, "Reset test", pltbutils_sc);
72
    waitclks(2, clk, pltbutils_sc);
73
    check("Sum during reset",       sum,         0, pltbutils_sc);
74
    check("Carry out during reset", carry_out, '0', pltbutils_sc);
75
    rst         <= '0';
76
 
77
    testname(2, "Simple sum test", pltbutils_sc);
78
    carry_in <= '0';
79
    x <= std_logic_vector(to_unsigned(1, x'length));
80
    y <= std_logic_vector(to_unsigned(2, x'length));
81
    waitclks(2, clk, pltbutils_sc);
82
    check("Sum",       sum,         3, pltbutils_sc);
83
    check("Carry out", carry_out, '0', pltbutils_sc);
84
 
85
    testname(3, "Simple carry in test", pltbutils_sc);
86 15 pela
    print(G_DISABLE_BUGS=0, pltbutils_sc, "Bug here somewhere");
87 2 pela
    carry_in <= '1';
88
    x <= std_logic_vector(to_unsigned(1, x'length));
89
    y <= std_logic_vector(to_unsigned(2, x'length));
90
    waitclks(2, clk, pltbutils_sc);
91
    check("Sum",       sum,         4, pltbutils_sc);
92
    check("Carry out", carry_out, '0', pltbutils_sc);
93
    print(pltbutils_sc, "");
94
 
95
    testname(4, "Simple carry out test", pltbutils_sc);
96
    carry_in <= '0';
97
    x <= std_logic_vector(to_unsigned(2**G_WIDTH-1, x'length));
98
    y <= std_logic_vector(to_unsigned(1, x'length));
99
    waitclks(2, clk, pltbutils_sc);
100
    check("Sum",       sum,         0, pltbutils_sc);
101
    check("Carry out", carry_out, '1', pltbutils_sc);
102
 
103
    endsim(pltbutils_sc, true);
104
    wait;
105
  end process p_tc1;
106
end architecture tc1;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.