OpenCores
URL https://opencores.org/ocsvn/pltbutils/pltbutils/trunk

Subversion Repositories pltbutils

[/] [pltbutils/] [branches/] [dev_beta0002/] [templates/] [vhdl/] [template2/] [tc1.vhd] - Blame information for rev 2

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 pela
----------------------------------------------------------------------
2
----                                                              ----
3
---- PlTbUtils Example Testcase Architecture for                  ----
4
---- Template Testbench                                            ----
5
----                                                              ----
6
---- This file is part of the PlTbUtils project                   ----
7
---- http://opencores.org/project,pltbutils                       ----
8
----                                                              ----
9
---- Description:                                                  ----
10
---- PlTbUtils is a collection of functions, procedures and       ----
11
---- components for easily creating stimuli and checking response ----
12
---- in automatic self-checking testbenches.                      ----
13
----                                                              ----
14
---- This file is an example which demonstrates how PlTbUtils     ----
15
---- can be used.                                                 ----
16
----                                                              ----
17
----                                                              ----
18
---- To Do:                                                       ----
19
---- -                                                            ----
20
----                                                              ----
21
---- Author(s):                                                   ----
22
---- - Per Larsson, pela@opencores.org                            ----
23
----                                                              ----
24
----------------------------------------------------------------------
25
----                                                              ----
26
---- Copyright (C) 2013 Authors and OPENCORES.ORG                 ----
27
----                                                              ----
28
---- This source file may be used and distributed without         ----
29
---- restriction provided that this copyright statement is not    ----
30
---- removed from the file and that any derivative work contains  ----
31
---- the original copyright notice and the associated disclaimer. ----
32
----                                                              ----
33
---- This source file is free software; you can redistribute it   ----
34
---- and/or modify it under the terms of the GNU Lesser General   ----
35
---- Public License as published by the Free Software Foundation; ----
36
---- either version 2.1 of the License, or (at your option) any   ----
37
---- later version.                                               ----
38
----                                                              ----
39
---- This source is distributed in the hope that it will be       ----
40
---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
41
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
42
---- PURPOSE. See the GNU Lesser General Public License for more  ----
43
---- details.                                                     ----
44
----                                                              ----
45
---- You should have received a copy of the GNU Lesser General    ----
46
---- Public License along with this source; if not, download it   ----
47
---- from http://www.opencores.org/lgpl.shtml                     ----
48
----                                                              ----
49
----------------------------------------------------------------------
50
library ieee;
51
use ieee.std_logic_1164.all;
52
use ieee.numeric_std.all;
53
use work.pltbutils_func_pkg.all;
54
 
55
architecture tc1 of tc_template is
56
begin
57
  p_tc1 : process
58
  begin
59
    startsim("tc1", pltbutils_sc);
60
    rst         <= '1'; -- Template example
61
    -- < Template info: initialize other DUT stimuli here. >
62
 
63
    testname(1, "Reset test", pltbutils_sc); -- Template example
64
    waitclks(2, clk, pltbutils_sc); -- Template example
65
    check("template_signal during reset", template_signal, 0, pltbutils_sc); -- Template example
66
    -- < Template info: check other DUT outputs here. 
67
    rst  <= '0'; -- Template example
68
 
69
    testname(2, "Template test", pltbutils_sc);
70
    -- < Template info: set all relevant DUT inputs here. >
71
    waitclks(2, clk, pltbutils_sc); -- Template example
72
    -- < Template info: check all relevant DUT outputs here. >
73
 
74
    -- < Template info: add more tests here. >
75
 
76
    endsim(pltbutils_sc, true);
77
    wait;
78
  end process p_tc1;
79
end architecture tc1;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.