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1 2 pela
----------------------------------------------------------------------
2
----                                                              ----
3
---- PlTbUtils Testbench                                          ----
4
----                                                              ----
5
---- This file is part of the PlTbUtils project                   ----
6
---- http://opencores.org/project,pltbutils                       ----
7
----                                                              ----
8
---- Description                                                  ----
9
---- PlTbUtils is a collection of functions, procedures and       ----
10
---- components for easily creating stimuli and checking response ----
11
---- in automatic self-checking testbenches.                      ----
12
----                                                              ----
13
---- This is a testbench file, which is used to verify            ----
14
---- - pltbutils_func_pkg                                         ----
15
---- - pltbutils_comp                                           ----
16
---- This testbench is NOT selfchecking or automatic.             ----
17
---- Manually check the transcript and waveform, when simulating. ----
18
---- It prints some informative text in the transcript, to help   ----
19
---- with the manual inspection.                                  ----
20
----                                                              ----
21
----                                                              ----
22
---- To Do:                                                       ----
23
---- -                                                            ----
24
----                                                              ----
25
---- Author(s):                                                   ----
26
---- - Per Larsson, pela@opencores.org                            ----
27
----                                                              ----
28
----------------------------------------------------------------------
29
----                                                              ----
30 38 pela
---- Copyright (C) 2013-2014 Authors and OPENCORES.ORG            ----
31 2 pela
----                                                              ----
32
---- This source file may be used and distributed without         ----
33
---- restriction provided that this copyright statement is not    ----
34
---- removed from the file and that any derivative work contains  ----
35
---- the original copyright notice and the associated disclaimer. ----
36
----                                                              ----
37
---- This source file is free software; you can redistribute it   ----
38
---- and/or modify it under the terms of the GNU Lesser General   ----
39
---- Public License as published by the Free Software Foundation; ----
40
---- either version 2.1 of the License, or (at your option) any   ----
41
---- later version.                                               ----
42
----                                                              ----
43
---- This source is distributed in the hope that it will be       ----
44
---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
45
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
46
---- PURPOSE. See the GNU Lesser General Public License for more  ----
47
---- details.                                                     ----
48
----                                                              ----
49
---- You should have received a copy of the GNU Lesser General    ----
50
---- Public License along with this source; if not, download it   ----
51
---- from http://www.opencores.org/lgpl.shtml                     ----
52
----                                                              ----
53
----------------------------------------------------------------------
54
library ieee;
55
use ieee.std_logic_1164.all;
56
use ieee.numeric_std.all;
57
use std.textio.all;
58
use work.txt_util.all;
59
use work.pltbutils_func_pkg.all;
60
use work.pltbutils_comp_pkg.all;
61
 
62
entity tb_pltbutils is
63
  generic (
64
    G_CLK_PERIOD  : time := 10 ns
65
  );
66
end entity tb_pltbutils;
67
 
68
architecture bhv of tb_pltbutils is
69
 
70
  -- Simulation status- and control signals
71 38 pela
  -- for accessing .stop_sim and for viewing in waveform window
72
  signal pltbs          : pltbs_t := C_PLTBS_INIT;
73 2 pela
 
74
  -- Expected number of checks and number of errors to be reported
75
  -- by pltbutils. The counting is made by variables, but the
76
  -- variables are copied to these signals for easier viewing in
77
  -- the simulator's waveform window.
78
  signal expected_checks_cnt : integer := 0;
79
  signal expected_errors_cnt : integer := 0;
80
 
81
  -- DUT stimuli and response signals
82
  signal clk            : std_logic;
83
  signal clk_cnt        : integer := 0;
84
  signal clk_cnt_clr    : boolean := false;
85
  signal s_i            : integer;
86
  signal s_sl           : std_logic;
87
  signal s_slv          : std_logic_vector(7 downto 0);
88
  signal s_u            : unsigned(7 downto 0);
89
  signal s_s            : unsigned(7 downto 0);
90 89 pela
  signal s_str_exp      : string(1 to 44);
91
  signal s_str1         : string(1 to 44);
92
  signal s_str2         : string(1 to 44);
93
  signal s_str3         : string(1 to 43);
94
  signal s_str4         : string(1 to 45);
95 2 pela
 
96
begin
97
 
98
  -- Clock generator
99
  clkgen0 : pltbutils_clkgen
100
    generic map(
101
      G_PERIOD      => G_CLK_PERIOD
102
    )
103
    port map(
104
      clk_o         => clk,
105 38 pela
      stop_sim_i    => pltbs.stop_sim
106 2 pela
    );
107
 
108
  -- Clock cycle counter
109
  p_clk_cnt : process (clk_cnt_clr, clk)
110
  begin
111
    if clk_cnt_clr then
112
      clk_cnt <= 0;
113
    elsif rising_edge(clk) then
114
      clk_cnt <= clk_cnt + 1;
115
    end if;
116
  end process p_clk_cnt;
117
 
118
  -- Testcase
119
  p_tc1 : process
120 38 pela
    variable pltbv                 : pltbv_t := C_PLTBV_INIT;
121 25 pela
    variable v_expected_tests_cnt  : integer := 0;
122 2 pela
    variable v_expected_checks_cnt : integer := 0;
123
    variable v_expected_errors_cnt : integer := 0;
124
  begin
125
 
126
    print("<Testing startsim()>");
127 38 pela
    startsim("tc1", pltbv, pltbs);
128 2 pela
    wait until rising_edge(clk);
129 38 pela
    assert (pltbv.test_num = 0) and (pltbs.test_num  = 0)
130 2 pela
      report "test_num after startsim() incorrect"
131
      severity error;
132
    print("<Done testing startsim()>");
133
 
134 25 pela
    print("<Testing starttest() with auto-incrementing test_num>");
135 38 pela
    starttest("TestName1", pltbv, pltbs);
136 25 pela
    v_expected_tests_cnt := v_expected_tests_cnt + 1;
137 2 pela
    wait until rising_edge(clk);
138 38 pela
    assert (pltbv.test_num = 1) and (pltbs.test_num  = 1)
139 25 pela
      report "test_num after starttest() incorrect"
140 2 pela
      severity error;
141 25 pela
    print("<Done testing starttest() with auto-incrementing test_num()>");
142 2 pela
 
143 25 pela
    print("<Testing endtest()>");
144 38 pela
    endtest(pltbv, pltbs);
145 25 pela
    print("<Done testing endtest()>");
146
 
147
    print("<Testing starttest() with explicit test_num>");
148 38 pela
    starttest(3, "TestName2", pltbv, pltbs);
149 25 pela
    v_expected_tests_cnt := v_expected_tests_cnt + 1;
150 2 pela
    wait until rising_edge(clk);
151 38 pela
    assert (pltbv.test_num = 3) and (pltbs.test_num  = 3)
152 2 pela
      report "test_num after startsim() incorrect"
153
      severity error;
154 25 pela
    print("<Done testing starttest() with explicit test_num>");
155 2 pela
 
156
    print("<Testing waitclks()>");
157
    clk_cnt_clr <= true;
158
    wait until rising_edge(clk);
159
    clk_cnt_clr <= false;
160
    wait until rising_edge(clk);
161 38 pela
    waitclks(10, clk, pltbv, pltbs);
162 2 pela
    assert clk_cnt = 10
163
      report "clk_cnt after waitclks() incorrect:" & integer'image(clk_cnt) &
164
             " expected:" & integer'image(10)
165
      severity error;
166
    print("<Done testing waitclks()>");
167
 
168
    print("<Testing check() integer>");
169
    s_i <= 0;
170
    wait until rising_edge(clk);
171 38 pela
    check("Testing correct integer = 0", s_i, 0, pltbv, pltbs);
172 2 pela
    v_expected_checks_cnt := v_expected_checks_cnt + 1;
173
    expected_checks_cnt   <= v_expected_checks_cnt;
174
    s_i <= 1;
175
    wait until rising_edge(clk);
176 38 pela
    check("Testing correct integer = 1", s_i, 1, pltbv, pltbs);
177 2 pela
    v_expected_checks_cnt := v_expected_checks_cnt + 1;
178
    expected_checks_cnt   <= v_expected_checks_cnt;
179
    s_i <= 17;
180
    wait until rising_edge(clk);
181 38 pela
    check("Testing incorrect integer = 17", s_i, 18, pltbv, pltbs);
182 2 pela
    v_expected_checks_cnt := v_expected_checks_cnt + 1;
183
    expected_checks_cnt   <= v_expected_checks_cnt;
184
    v_expected_errors_cnt := v_expected_errors_cnt + 1;
185
    expected_errors_cnt   <= v_expected_errors_cnt;
186
    s_i <= -1;
187
    wait until rising_edge(clk);
188 38 pela
    check("Testing negative integer = -1", s_i, -1, pltbv, pltbs);
189 2 pela
    v_expected_checks_cnt := v_expected_checks_cnt + 1;
190
    expected_checks_cnt   <= v_expected_checks_cnt;
191
 
192
    print("<Done testing check() integer>");
193
 
194
    print("<Testing check() std_logic>");
195
    s_sl <= '0';
196
    wait until rising_edge(clk);
197 38 pela
    check("Testing correct std_logic = '0'", s_sl, '0', pltbv, pltbs);
198 2 pela
    v_expected_checks_cnt := v_expected_checks_cnt + 1;
199
    expected_checks_cnt   <= v_expected_checks_cnt;
200
    s_sl <= '1';
201
    wait until rising_edge(clk);
202 38 pela
    check("Testing correct std_logic = '1'", s_sl, '1', pltbv, pltbs);
203 2 pela
    v_expected_checks_cnt := v_expected_checks_cnt + 1;
204
    expected_checks_cnt   <= v_expected_checks_cnt;
205
    s_sl <= 'X';
206
    wait until rising_edge(clk);
207 38 pela
    check("Testing incorrect std_logic = '1'", s_sl, '1', pltbv, pltbs);
208 2 pela
    v_expected_checks_cnt := v_expected_checks_cnt + 1;
209
    expected_checks_cnt   <= v_expected_checks_cnt;
210
    v_expected_errors_cnt := v_expected_errors_cnt + 1;
211
    expected_errors_cnt   <= v_expected_errors_cnt;
212
    print("<Done testing check() std_logic>");
213
 
214
    print("<Testing check() std_logic against integer>");
215
    s_sl <= '0';
216
    wait until rising_edge(clk);
217 38 pela
    check("Testing correct std_logic = '0'", s_sl, 0, pltbv, pltbs);
218 2 pela
    v_expected_checks_cnt := v_expected_checks_cnt + 1;
219
    expected_checks_cnt   <= v_expected_checks_cnt;
220
    s_sl <= '1';
221
    wait until rising_edge(clk);
222 38 pela
    check("Testing correct std_logic = '1'", s_sl, 1, pltbv, pltbs);
223 2 pela
    v_expected_checks_cnt := v_expected_checks_cnt + 1;
224
    expected_checks_cnt   <= v_expected_checks_cnt;
225
    s_sl <= 'X';
226
    wait until rising_edge(clk);
227 38 pela
    check("Testing incorrect std_logic = '1'", s_sl, 1, pltbv, pltbs);
228 2 pela
    v_expected_checks_cnt := v_expected_checks_cnt + 1;
229
    expected_checks_cnt   <= v_expected_checks_cnt;
230
    v_expected_errors_cnt := v_expected_errors_cnt + 1;
231
    expected_errors_cnt   <= v_expected_errors_cnt;
232
    s_sl <= '1';
233
    wait until rising_edge(clk);
234 38 pela
    check("Testing std_logic = '1' with incorrect expected", s_sl, 2, pltbv, pltbs);
235 2 pela
    v_expected_checks_cnt := v_expected_checks_cnt + 1;
236
    expected_checks_cnt   <= v_expected_checks_cnt;
237
    v_expected_errors_cnt := v_expected_errors_cnt + 1;
238
    expected_errors_cnt   <= v_expected_errors_cnt;
239
    print("<Done testing check() std_logic against integer>");
240
 
241
    print("<Testing check() std_logic_vector>");
242
    s_slv <= x"00";
243
    wait until rising_edge(clk);
244 38 pela
    check("Testing correct std_logic_vector = x'00'", s_slv, x"00", pltbv, pltbs);
245 2 pela
    v_expected_checks_cnt := v_expected_checks_cnt + 1;
246
    expected_checks_cnt   <= v_expected_checks_cnt;
247
    s_slv <= x"47";
248
    wait until rising_edge(clk);
249 38 pela
    check("Testing correct std_logic_vector = x'47'", s_slv, x"47", pltbv, pltbs);
250 2 pela
    v_expected_checks_cnt := v_expected_checks_cnt + 1;
251
    expected_checks_cnt   <= v_expected_checks_cnt;
252
    s_slv <= x"11";
253
    wait until rising_edge(clk);
254 38 pela
    check("Testing incorrect std_logic_vector = x'11'", s_slv, x"10", pltbv, pltbs);
255 2 pela
    v_expected_checks_cnt := v_expected_checks_cnt + 1;
256
    expected_checks_cnt   <= v_expected_checks_cnt;
257
    v_expected_errors_cnt := v_expected_errors_cnt + 1;
258
    expected_errors_cnt   <= v_expected_errors_cnt;
259
    print("<Done testing check() std_logic_vector>");
260
 
261
    print("<Testing check() std_logic_vector with mask>");
262
    s_slv <= x"47";
263
    wait until rising_edge(clk);
264 38 pela
    check("Testing std_logic_vector = x'47' with correct nibble mask", s_slv, x"57", x"0F", pltbv, pltbs);
265 2 pela
    v_expected_checks_cnt := v_expected_checks_cnt + 1;
266
    expected_checks_cnt   <= v_expected_checks_cnt;
267
    s_slv <= x"47";
268
    wait until rising_edge(clk);
269 38 pela
    check("Testing std_logic_vector = x'47' with incorrect nibble mask", s_slv, x"57", x"F0", pltbv, pltbs);
270 2 pela
    v_expected_checks_cnt := v_expected_checks_cnt + 1;
271
    expected_checks_cnt   <= v_expected_checks_cnt;
272
    v_expected_errors_cnt := v_expected_errors_cnt + 1;
273
    expected_errors_cnt   <= v_expected_errors_cnt;
274
    print("<Done testing check() std_logic_vector with mask>");
275
 
276
    print("<Testing check() std_logic_vector against integer>");
277
    s_slv <= x"00";
278
    wait until rising_edge(clk);
279 38 pela
    check("Testing correct std_logic_vector = x'00'", s_slv, 0, pltbv, pltbs);
280 2 pela
    v_expected_checks_cnt := v_expected_checks_cnt + 1;
281
    expected_checks_cnt   <= v_expected_checks_cnt;
282
    s_slv <= x"47";
283
    wait until rising_edge(clk);
284 38 pela
    check("Testing correct std_logic_vector = x'47'", s_slv, 16#47#, pltbv, pltbs);
285 2 pela
    v_expected_checks_cnt := v_expected_checks_cnt + 1;
286
    expected_checks_cnt   <= v_expected_checks_cnt;
287
    s_slv <= x"11";
288
    wait until rising_edge(clk);
289 38 pela
    check("Testing incorrect std_logic_vector = x'11'", s_slv, 16#10#, pltbv, pltbs);
290 2 pela
    v_expected_checks_cnt := v_expected_checks_cnt + 1;
291
    expected_checks_cnt   <= v_expected_checks_cnt;
292
    v_expected_errors_cnt := v_expected_errors_cnt + 1;
293
    expected_errors_cnt   <= v_expected_errors_cnt;
294
    s_slv <= x"FF";
295
    wait until rising_edge(clk);
296 38 pela
    check("Testing negative std_logic_vector = x'FF'", s_slv, -1, pltbv, pltbs);
297 2 pela
    v_expected_checks_cnt := v_expected_checks_cnt + 1;
298
    expected_checks_cnt   <= v_expected_checks_cnt;
299
    print("<Done testing check() std_logic_vector against integer>");
300
 
301
    print("<Testing check() std_logic_vector with mask against integer>");
302
    s_slv <= x"47";
303
    wait until rising_edge(clk);
304 38 pela
    check("Testing std_logic_vector = x'47' with correct nibble mask", s_slv, 16#57#, x"0F", pltbv, pltbs);
305 2 pela
    v_expected_checks_cnt := v_expected_checks_cnt + 1;
306
    expected_checks_cnt   <= v_expected_checks_cnt;
307
    s_slv <= x"47";
308
    wait until rising_edge(clk);
309 38 pela
    check("Testing std_logic_vector = x'47' with incorrect nibble mask", s_slv, 16#57#, x"F0", pltbv, pltbs);
310 2 pela
    v_expected_checks_cnt := v_expected_checks_cnt + 1;
311
    expected_checks_cnt   <= v_expected_checks_cnt;
312
    v_expected_errors_cnt := v_expected_errors_cnt + 1;
313
    expected_errors_cnt   <= v_expected_errors_cnt;
314
    print("<Done testing check() std_logic_vector with mask against integer>");
315
 
316
    print("<Testing check() unsigned>");
317
    s_u <= x"00";
318
    wait until rising_edge(clk);
319 38 pela
    check("Testing correct unsigned = x'00'", s_u, x"00", pltbv, pltbs);
320 2 pela
    v_expected_checks_cnt := v_expected_checks_cnt + 1;
321
    expected_checks_cnt   <= v_expected_checks_cnt;
322
    s_u <= x"47";
323
    wait until rising_edge(clk);
324 38 pela
    check("Testing correct unsigned = x'47'", s_u, x"47", pltbv, pltbs);
325 2 pela
    v_expected_checks_cnt := v_expected_checks_cnt + 1;
326
    expected_checks_cnt   <= v_expected_checks_cnt;
327
    s_u <= x"11";
328
    wait until rising_edge(clk);
329 38 pela
    check("Testing incorrect unsigned = x'11'", s_u, x"10", pltbv, pltbs);
330 2 pela
    v_expected_checks_cnt := v_expected_checks_cnt + 1;
331
    expected_checks_cnt   <= v_expected_checks_cnt;
332
    v_expected_errors_cnt := v_expected_errors_cnt + 1;
333
    expected_errors_cnt   <= v_expected_errors_cnt;
334
    print("<Done testing check() unsigned>");
335
 
336
    print("<Testing check() unsigned against integer>");
337
    s_u <= x"00";
338
    wait until rising_edge(clk);
339 38 pela
    check("Testing correct unsigned = x'00'", s_u, 0, pltbv, pltbs);
340 2 pela
    v_expected_checks_cnt := v_expected_checks_cnt + 1;
341
    expected_checks_cnt   <= v_expected_checks_cnt;
342
    s_u <= x"47";
343
    wait until rising_edge(clk);
344 38 pela
    check("Testing correct unsigned = x'47'", s_u, 16#47#, pltbv, pltbs);
345 2 pela
    v_expected_checks_cnt := v_expected_checks_cnt + 1;
346
    expected_checks_cnt   <= v_expected_checks_cnt;
347
    s_u <= x"11";
348
    wait until rising_edge(clk);
349 38 pela
    check("Testing incorrect unsigned = x'11'", s_u, 16#10#, pltbv, pltbs);
350 2 pela
    v_expected_checks_cnt := v_expected_checks_cnt + 1;
351
    expected_checks_cnt   <= v_expected_checks_cnt;
352
    v_expected_errors_cnt := v_expected_errors_cnt + 1;
353
    expected_errors_cnt   <= v_expected_errors_cnt;
354
    print("<Done testing check() unsigned against integer>");
355
 
356
    print("<Testing check() signed>");
357
    s_s <= x"00";
358
    wait until rising_edge(clk);
359 38 pela
    check("Testing correct signed = x'00'", s_s, x"00", pltbv, pltbs);
360 2 pela
    v_expected_checks_cnt := v_expected_checks_cnt + 1;
361
    expected_checks_cnt   <= v_expected_checks_cnt;
362
    s_s <= x"47";
363
    wait until rising_edge(clk);
364 38 pela
    check("Testing correct signed = x'47'", s_s, x"47", pltbv, pltbs);
365 2 pela
    v_expected_checks_cnt := v_expected_checks_cnt + 1;
366
    expected_checks_cnt   <= v_expected_checks_cnt;
367
    s_s <= x"11";
368
    wait until rising_edge(clk);
369 38 pela
    check("Testing incorrect signed = x'11'", s_s, x"10", pltbv, pltbs);
370 2 pela
    v_expected_checks_cnt := v_expected_checks_cnt + 1;
371
    expected_checks_cnt   <= v_expected_checks_cnt;
372
    v_expected_errors_cnt := v_expected_errors_cnt + 1;
373
    expected_errors_cnt   <= v_expected_errors_cnt;
374
    s_s <= x"FF";
375
    wait until rising_edge(clk);
376 38 pela
    check("Testing negative signed = x'FF'", s_s, x"FF", pltbv, pltbs);
377 2 pela
    v_expected_checks_cnt := v_expected_checks_cnt + 1;
378
    expected_checks_cnt   <= v_expected_checks_cnt;
379
    print("<Done testing check() signed>");
380
 
381
    print("<Testing check() signed against integer>");
382
    s_s <= x"00";
383
    wait until rising_edge(clk);
384 38 pela
    check("Testing correct signed = x'00'", s_s, 0, pltbv, pltbs);
385 2 pela
    v_expected_checks_cnt := v_expected_checks_cnt + 1;
386
    expected_checks_cnt   <= v_expected_checks_cnt;
387
    s_s <= x"47";
388
    wait until rising_edge(clk);
389 38 pela
    check("Testing correct signed = x'47'", s_s, 16#47#, pltbv, pltbs);
390 2 pela
    v_expected_checks_cnt := v_expected_checks_cnt + 1;
391
    expected_checks_cnt   <= v_expected_checks_cnt;
392
    s_s <= x"11";
393
    wait until rising_edge(clk);
394 38 pela
    check("Testing incorrect signed = x'11'", s_s, 16#10#, pltbv, pltbs);
395 2 pela
    v_expected_checks_cnt := v_expected_checks_cnt + 1;
396
    expected_checks_cnt   <= v_expected_checks_cnt;
397
    v_expected_errors_cnt := v_expected_errors_cnt + 1;
398
    expected_errors_cnt   <= v_expected_errors_cnt;
399
    s_s <= x"FF";
400
    wait until rising_edge(clk);
401
    print("The following check fails in ModelSim for unknown reason." &
402
          " It causes mismatch between expected number of errors" &
403
          " and the number presented by endsim()");
404 38 pela
    check("Testing negative signed = x'FF'", s_s, -1, pltbv, pltbs);
405 2 pela
    v_expected_checks_cnt := v_expected_checks_cnt + 1;
406
    expected_checks_cnt   <= v_expected_checks_cnt;
407
    print("<Done testing check() signed against integer>");
408
 
409 89 pela
    print("<Testing check() string>");
410
    s_str_exp   <= string'("The quick brown fox jumps over the lazy dog.");
411
    s_str1      <= string'("The quick brown fox jumps over the lazy dog.");
412
    s_str2      <= string'("The quick brown dog jumps over the lazy fox.");
413
    s_str3      <= string'("The quick brown fox jumps over the lazy dog");
414
    s_str4      <= string'("The quick brown fox jumps over the lazy dog..");
415
    wait until rising_edge(clk);
416
    check("Testing correct string", s_str1, s_str_exp, pltbv, pltbs);
417
    v_expected_checks_cnt := v_expected_checks_cnt + 1;
418
    expected_checks_cnt   <= v_expected_checks_cnt;
419
    s_s <= x"47";
420
    wait until rising_edge(clk);
421
    check("Testing incorrect string with correct length", s_str2, s_str_exp, pltbv, pltbs);
422
    v_expected_checks_cnt := v_expected_checks_cnt + 1;
423
    expected_checks_cnt   <= v_expected_checks_cnt;
424
    v_expected_errors_cnt := v_expected_errors_cnt + 1;
425
    expected_errors_cnt   <= v_expected_errors_cnt;
426
    s_s <= x"11";
427
    wait until rising_edge(clk);
428
    check("Testing too short string", s_str3, s_str_exp, pltbv, pltbs);
429
    v_expected_checks_cnt := v_expected_checks_cnt + 1;
430
    expected_checks_cnt   <= v_expected_checks_cnt;
431
    v_expected_errors_cnt := v_expected_errors_cnt + 1;
432
    expected_errors_cnt   <= v_expected_errors_cnt;
433
    wait until rising_edge(clk);
434
    check("Testing too long string", s_str4, s_str_exp, pltbv, pltbs);
435
    v_expected_checks_cnt := v_expected_checks_cnt + 1;
436
    expected_checks_cnt   <= v_expected_checks_cnt;
437
    v_expected_errors_cnt := v_expected_errors_cnt + 1;
438
    expected_errors_cnt   <= v_expected_errors_cnt;
439
    print("<Done testing check() string>");
440
 
441 2 pela
    print("<Testing check() boolean expression>");
442
    s_i <= 0;
443
    wait until rising_edge(clk);
444 38 pela
    check("Testing correct boolean expression 0 = 16#00#", s_i = 16#00#, pltbv, pltbs);
445 2 pela
    v_expected_checks_cnt := v_expected_checks_cnt + 1;
446
    expected_checks_cnt   <= v_expected_checks_cnt;
447
    s_i <= 47;
448
    wait until rising_edge(clk);
449 38 pela
    check("Testing incorrect boolean expression 47 < 16#10#", s_i < 16#10#, pltbv, pltbs);
450 2 pela
    v_expected_checks_cnt := v_expected_checks_cnt + 1;
451
    expected_checks_cnt   <= v_expected_checks_cnt;
452
    v_expected_errors_cnt := v_expected_errors_cnt + 1;
453
    expected_errors_cnt   <= v_expected_errors_cnt;
454
    print("<Done testing check() boolean expresson>");
455 25 pela
 
456
    print("<Testing endtest()>");
457 38 pela
    endtest(pltbv, pltbs);
458 25 pela
    print("<Done testing endtest()>");
459 2 pela
 
460
    wait until rising_edge(clk);
461
    print("<Testing endsim()>");
462 25 pela
    print("Expected number of tests:  " & str(v_expected_tests_cnt));
463 2 pela
    print("Expected number of checks: " & str(v_expected_checks_cnt));
464
    print("Expected number of errors: " & str(v_expected_errors_cnt));
465
    wait until rising_edge(clk);
466 38 pela
    endsim(pltbv, pltbs, true);
467 2 pela
    wait until rising_edge(clk);
468
    print("<Done testing endsim()>");
469
    wait;
470
  end process p_tc1;
471
end architecture bhv;

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